公开(公告)号：US20200273982A1

公开(公告)日：2020-08-27

申请号：US16872501

申请日：2020-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Wai Ng ,  Hsueh-Liang Chou ,  Po-Chih Su ,  Ruey-Hsin Liu

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06

Abstract: A method includes forming a first semiconductor layer over a substrate, forming a second semiconductor layer over the first semiconductor layer, forming a first trench and a second trench through in the first semiconductor layer and the second semiconductor layer, wherein a width of the second trench is different from a width of the first trench, forming a dielectric region in the first trench and forming a first gate region in the first trench and over the dielectric region, and a second gate region in the second trench.

公开(公告)号：US11424244B2

公开(公告)日：2022-08-23

申请号：US17088711

申请日：2020-11-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Wai Ng ,  Hsueh-Liang Chou ,  Po-Chih Su ,  Ruey-Hsin Liu

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/306 ,  H01L21/762 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

Abstract: A device includes a vertical transistor comprising a first gate in a first trench, wherein the first gate comprises a dielectric layer and a gate region over the dielectric layer, and a second gate in a second trench, a high voltage lateral transistor immediately adjacent to the vertical transistor and a low voltage lateral transistor, wherein the high voltage lateral transistor is between the vertical transistor and the low voltage lateral transistor.

公开(公告)号：US11031495B2

公开(公告)日：2021-06-08

申请号：US16872501

申请日：2020-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Wai Ng ,  Hsueh-Liang Chou ,  Po-Chih Su ,  Ruey-Hsin Liu

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06

Abstract: A method includes forming a first semiconductor layer over a substrate, forming a second semiconductor layer over the first semiconductor layer, forming a first trench and a second trench through in the first semiconductor layer and the second semiconductor layer, wherein a width of the second trench is different from a width of the first trench, forming a dielectric region in the first trench and forming a first gate region in the first trench and over the dielectric region, and a second gate region in the second trench.

公开(公告)号：US20210057412A1

公开(公告)日：2021-02-25

申请号：US17088711

申请日：2020-11-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Wai Ng ,  Hsueh-Liang Chou ,  Po-Chih Su ,  Ruey-Hsin Liu

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

Abstract: A device includes a vertical transistor comprising a first gate in a first trench, wherein the first gate comprises a dielectric layer and a gate region over the dielectric layer, and a second gate in a second trench, a high voltage lateral transistor immediately adjacent to the vertical transistor and a low voltage lateral transistor, wherein the high voltage lateral transistor is between the vertical transistor and the low voltage lateral transistor.