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    Plate design to decrease noise in semiconductor devices
    1.
    发明授权
    Plate design to decrease noise in semiconductor devices 有权

    公开(公告)号：US11107899B2

    公开(公告)日：2021-08-31

    申请号：US16837401

    申请日：2020-04-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ming-Ta Lei ,  Ruey-Hsin Liu ,  Shih-Fen Huang

    IPC: H01L29/78 ,  H01L29/423 ,  H01L21/265 ,  H01L21/28 ,  H01L29/06 ,  H01L29/08 ,  H01L29/49

    Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

    Selective polysilicon doping for gate induced drain leakage improvement
    3.
    发明授权
    Selective polysilicon doping for gate induced drain leakage improvement 有权

    公开(公告)号：US10680019B2

    公开(公告)日：2020-06-09

    申请号：US16382455

    申请日：2019-04-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Liang Chu ,  Chih-Wen Albert Yao ,  Ruey-Hsin Liu ,  Ming-Ta Lei

    IPC: H01L27/12 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

    Abstract: Some embodiments of the present disclosure relate to a method of forming a transistor. The method includes forming a gate dielectric over a substrate and forming a gate over the gate dielectric. The gate includes polysilicon extending between a first outermost sidewall and a second outermost sidewall of the gate. A mask is formed over the gate. The mask exposes a first gate region extending to the first outermost sidewall and covers a second gate region extending between the first gate region and the second outermost sidewall. Dopants are selectively implanted into the first gate region according to the mask. Source and drain regions are formed within the substrate. The source region and the drain region are asymmetric with respect to an interface of the first gate region and the second gate region and extend to substantially equal distances past the first and second outermost sidewalls of the gate, respectively.

    Enhanced breakdown voltages for high voltage MOSFETS
    4.
    发明授权
    Enhanced breakdown voltages for high voltage MOSFETS 有权
    高压MOSFET的增强击穿电压

    公开(公告)号：US09412863B2

    公开(公告)日：2016-08-09

    申请号：US14580636

    申请日：2014-12-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsin-Chih Chiang ,  Tung-Yang Lin ,  Ruey-Hsin Liu ,  Ming-Ta Lei

    IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40

    CPC classification number: H01L29/7824 ,  H01L29/0626 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/401 ,  H01L29/402 ,  H01L29/66681

    Abstract: An integrated circuit (IC) includes a high-voltage (HV) MOSFET on a substrate. The substrate includes a handle substrate region, an insulating region, and a silicon region. Source region and drain regions, which have a first conductivity type, are disposed in the silicon region and spaced apart from one another. A gate electrode is disposed over an upper region of the silicon region and is arranged between the source and drain regions. A body region, which has a second conductivity type, is arranged under the gate electrode and separates the source and drain regions. A lateral drain extension region, which has the first conductivity type, is disposed in the upper region of the silicon region and extends laterally between the body and drain regions. A breakdown voltage enhancing region, which has the second conductivity type, is disposed in the silicon region under the lateral drain extension region.

    Abstract translation: 集成电路（IC）包括在基板上的高压（HV）MOSFET。 基板包括手柄基板区域，绝缘区域和硅区域。 具有第一导电类型的源极区和漏极区被布置在硅区域中并彼此间隔开。 栅电极设置在硅区域的上部区域上并且布置在源区域和漏极区域之间。 具有第二导电类型的体区被布置在栅电极下方并分离源区和漏区。 具有第一导电类型的横向漏极延伸区域设置在硅区域的上部区域中，并且在主体区域和漏极区域之间横向延伸。 具有第二导电类型的击穿电压增强区域设置在侧向漏极延伸区域下方的硅区域中。

    Plate design to decrease noise in semiconductor devices
    9.
    发明授权
    Plate design to decrease noise in semiconductor devices 有权

    公开(公告)号：US11011610B2

    公开(公告)日：2021-05-18

    申请号：US16837444

    申请日：2020-04-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ming-Ta Lei ,  Ruey-Hsin Liu ,  Shih-Fen Huang

    IPC: H01L29/78 ,  H01L29/423 ,  H01L21/265 ,  H01L21/28 ,  H01L29/06 ,  H01L29/08 ,  H01L29/49

    Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

    PLATE DESIGN TO DECREASE NOISE IN SEMICONDUCTOR DEVICES
    10.
    发明申请
    PLATE DESIGN TO DECREASE NOISE IN SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20200227529A1

    公开(公告)日：2020-07-16

    申请号：US16837444

    申请日：2020-04-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ming-Ta Lei ,  Ruey-Hsin Liu ,  Shih-Fen Huang

    IPC: H01L29/423 ,  H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L29/06 ,  H01L29/08

    Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

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