公开(公告)号：US20240079239A1

公开(公告)日：2024-03-07

申请号：US18152454

申请日：2023-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bau-Ming Wang ,  Liang-Yin Chen ,  Wei Tse Hsu ,  Jung-Tsan Tsai ,  Ya-Ching Tseng ,  Chunyii Liu

IPC: H01L21/225 ,  H01L21/306 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L21/2253 ,  H01L21/30625 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/0673

Abstract: A method includes implanting impurities in a semiconductor substrate to form an etch stop region within the semiconductor substrate; forming a transistor structure on a front side of the semiconductor substrate; forming a front-side interconnect structure over the transistor structure; performing a thinning process on a back side of the semiconductor substrate to reduce a thickness of the semiconductor substrate, wherein the thinning process is slowed by the etch stop region; and forming a back-side interconnect structure over the back side of the semiconductor substrate.