公开(公告)号：US11495674B2

公开(公告)日：2022-11-08

申请号：US16725802

申请日：2019-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ling Chan ,  Derek Chen ,  Liang-Yin Chen ,  Chien-I Kuo

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L21/02 ,  H01L21/225 ,  H01L21/324

Abstract: A method of forming source/drain features in a FinFET device includes providing a fin formed over a substrate and a gate structure formed over a fin, forming a recess in the fin adjacent to the gate structure, forming a first epitaxial layer in the recess, forming a second epitaxial layer over the first epitaxial layer, and forming a third epitaxial layer over the second epitaxial layer. The second epitaxial layer may be doped with a first element, while one or both of the first and the third epitaxial layer includes a second element different from the first element. One or both of the first and the third epitaxial layer may be formed by a plasma deposition process.

公开(公告)号：US20230058699A1

公开(公告)日：2023-02-23

申请号：US17982216

申请日：2022-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ling Chan ,  Derek Chen ,  Liang-Yin Chen ,  Chien-I Kuo

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L21/02 ,  H01L21/225 ,  H01L21/324

Abstract: A method of forming source/drain features in a FinFET device includes providing a fin formed over a substrate and a gate structure formed over a fin, forming a recess in the fin adjacent to the gate structure, forming a first epitaxial layer in the recess, forming a second epitaxial layer over the first epitaxial layer, and forming a third epitaxial layer over the second epitaxial layer. The second epitaxial layer may be doped with a first element, while one or both of the first and the third epitaxial layer includes a second element different from the first element. One or both of the first and the third epitaxial layer may be formed by a plasma deposition process.

公开(公告)号：US10522656B2

公开(公告)日：2019-12-31

申请号：US15907427

申请日：2018-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ling Chan ,  Derek Chen ,  Liang-Yin Chen ,  Chien-I Kuo

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L21/02 ,  H01L21/225 ,  H01L21/324

Abstract: A method of forming source/drain features in a FinFET device includes providing a fin formed over a substrate and a gate structure formed over a fin, forming a recess in the fin adjacent to the gate structure, forming a first epitaxial layer in the recess, forming a second epitaxial layer over the first epitaxial layer, and forming a third epitaxial layer over the second epitaxial layer. The second epitaxial layer may be doped with a first element, while one or both of the first and the third epitaxial layer includes a second element different from the first element. One or both of the first and the third epitaxial layer may be formed by a plasma deposition process.

公开(公告)号：US20190267471A1

公开(公告)日：2019-08-29

申请号：US15907427

申请日：2018-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ling Chan ,  Derek Chen ,  Liang-Yin Chen ,  Chien-I Kuo

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L21/02 ,  H01L21/225 ,  H01L21/324

Abstract: A method of forming source/drain features in a FinFET device includes providing a fin formed over a substrate and a gate structure formed over a fin, forming a recess in the fin adjacent to the gate structure, forming a first epitaxial layer in the recess, forming a second epitaxial layer over the first epitaxial layer, and forming a third epitaxial layer over the second epitaxial layer. The second epitaxial layer may be doped with a first element, while one or both of the first and the third epitaxial layer includes a second element different from the first element. One or both of the first and the third epitaxial layer may be formed by a plasma deposition process.