公开(公告)号：US20230058699A1

公开(公告)日：2023-02-23

申请号：US17982216

申请日：2022-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ling Chan ,  Derek Chen ,  Liang-Yin Chen ,  Chien-I Kuo

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L21/02 ,  H01L21/225 ,  H01L21/324

Abstract: A method of forming source/drain features in a FinFET device includes providing a fin formed over a substrate and a gate structure formed over a fin, forming a recess in the fin adjacent to the gate structure, forming a first epitaxial layer in the recess, forming a second epitaxial layer over the first epitaxial layer, and forming a third epitaxial layer over the second epitaxial layer. The second epitaxial layer may be doped with a first element, while one or both of the first and the third epitaxial layer includes a second element different from the first element. One or both of the first and the third epitaxial layer may be formed by a plasma deposition process.

公开(公告)号：US10861935B2

公开(公告)日：2020-12-08

申请号：US16531421

申请日：2019-08-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-I Kuo ,  Shao-Fu Fu ,  Chia-Ling Chan ,  Yi-Fang Pai ,  Li-Li Su ,  Wei Hao Lu ,  Wei Te Chiang ,  Chii-Horng Li

IPC: H01L29/08 ,  H01L29/167 ,  H01L29/36 ,  H01L21/223 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/22 ,  H01L21/3065 ,  H01L21/306

Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.

公开(公告)号：US10566242B2

公开(公告)日：2020-02-18

申请号：US15376719

申请日：2016-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ling Chan ,  Tsan-Chun Wang ,  Liang-Yin Chen ,  Huicheng Chang

IPC: H01L21/8234 ,  H01L21/223 ,  H01L29/66

Abstract: A plasma doping process provides conformal doping profiles for lightly doped source/drain regions in fins, and reduces the plasma doping induced fin height loss. The plasma doping process overcomes the limitations caused by traditional plasma doping processes in fin structures that feature aggressive aspect ratios and tights pitches. Semiconductor devices with conformal lightly doped S/D regions and reduced fin height loss demonstrate reduced parallel resistance (Rp) and improved transistor performance.

公开(公告)号：US10522656B2

公开(公告)日：2019-12-31

申请号：US15907427

申请日：2018-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ling Chan ,  Derek Chen ,  Liang-Yin Chen ,  Chien-I Kuo

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L21/02 ,  H01L21/225 ,  H01L21/324

Abstract: A method of forming source/drain features in a FinFET device includes providing a fin formed over a substrate and a gate structure formed over a fin, forming a recess in the fin adjacent to the gate structure, forming a first epitaxial layer in the recess, forming a second epitaxial layer over the first epitaxial layer, and forming a third epitaxial layer over the second epitaxial layer. The second epitaxial layer may be doped with a first element, while one or both of the first and the third epitaxial layer includes a second element different from the first element. One or both of the first and the third epitaxial layer may be formed by a plasma deposition process.

公开(公告)号：US20210013337A1

公开(公告)日：2021-01-14

申请号：US17027078

申请日：2020-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ling Chan ,  Yen-Chun Lin

IPC: H01L29/78 ,  H01L21/22 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L23/532 ,  H01L29/423 ,  H01L21/768 ,  H01L21/308 ,  H01L21/8238 ,  H01L21/324

Abstract: A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, forming a first spacer over the dummy gate structure, implanting a first dopant in the fin to form a doped region of the fin adjacent the first spacer, removing the doped region of the fin to form a first recess, wherein the first recess is self-aligned to the doped region, and epitaxially growing a source/drain region in the first recess.

公开(公告)号：US20200343383A1

公开(公告)日：2020-10-29

申请号：US16923686

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yang Lee ,  Chia-Chun Lan ,  Chia-Ling Chan ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/08 ,  H01L29/167 ,  H01L29/66 ,  H01L21/311 ,  H01L27/092 ,  H01L21/8238

Abstract: A semiconductor device includes a fin structure disposed on a substrate, a shallow-trench isolation (STI) region on opposite sides of the fin structure, dielectric fin sidewall structures extending along sides of the fin structure and extending from a top of the STI region partially up the fin structure, and a source/drain region disposed within an upper portion of the fin structure. A bottom surface of the source/drain region contacts a top surface of the dielectric fin sidewall.

公开(公告)号：US20180175200A1

公开(公告)日：2018-06-21

申请号：US15460006

申请日：2017-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Wei-Yang Lee ,  Chia-Chun Lan ,  Chia-Ling Chan ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/08 ,  H01L29/167 ,  H01L29/66 ,  H01L21/311 ,  H01L27/092

CPC classification number: H01L29/7851 ,  H01L21/31111 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66803

Abstract: A system is configured to perform plasma related fabrication processes. The system includes a process chamber and a wafer stage positioned within the process chamber. The wafer stage is configured to secure a process wafer. The system further includes a bottom electrode positioned beneath the wafer stage, a top electrode positioned external to the chamber, and a plasma distribution mechanism. The plasma distribution mechanism is reconfigurable to allow for more than one plasma distribution profile.

公开(公告)号：US09343575B1

公开(公告)日：2016-05-17

申请号：US14819602

申请日：2015-08-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang Lee ,  Ting-Yeh Chen ,  Chia-Ling Chan ,  Chien-Tai Chan

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7851 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/785

Abstract: A FinFET includes a fin structure, a gate and a source-drain region. The fin structure is over a substrate and has a recess of an upper surface of the fin structure and a doped region in the fin structure and adjacent to the recess. The gate protrudes from the recess and across over the fin structure. The source-drain region is in the fin structure and adjacent to the doped region. Methods for forming the FinFET are also provided.

公开(公告)号：US11677028B2

公开(公告)日：2023-06-13

申请号：US16923686

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yang Lee ,  Chia-Chun Lan ,  Chia-Ling Chan ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/08 ,  H01L29/167 ,  H01L29/66 ,  H01L21/311 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/7851 ,  H01L21/31111 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/66803 ,  H01L21/823814

Abstract: A semiconductor device includes a fin structure disposed on a substrate, a shallow-trench isolation (STI) region on opposite sides of the fin structure, dielectric fin sidewall structures extending along sides of the fin structure and extending from a top of the STI region partially up the fin structure, and a source/drain region disposed within an upper portion of the fin structure. A bottom surface of the source/drain region contacts a top surface of the dielectric fin sidewall.

公开(公告)号：US20180337282A1

公开(公告)日：2018-11-22

申请号：US16046740

申请日：2018-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yang Lee ,  Chia-Chun Lan ,  Chia-Ling Chan ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/167 ,  H01L21/311 ,  H01L29/08 ,  H01L27/092 ,  H01L29/161

Abstract: A method for fabricating a semiconductor device includes forming a doped semiconductor layer on a substrate and forming a fin structure disposed on the doped semiconductor layer. The fin structure is doped with a p-type dopant. The method further includes forming a source/drain region within an upper portion of the fin structure and forming a fin sidewall along a lower portion of the fin structure. The fin sidewall has the p-type dopant.