公开(公告)号：US10978449B2

公开(公告)日：2021-04-13

申请号：US16723938

申请日：2019-12-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Hui Chen ,  Hao-Chieh Chan ,  Wei-Chih Chen

IPC: H01L27/108 ,  H01L27/06 ,  H01L49/02 ,  H01L27/02 ,  H01L23/522 ,  H01L23/528

Abstract: A device includes a plurality of active areas, a plurality of gates, and a plurality of conductors. The active areas are elongated in a first direction. The gates are elongated in a second direction. The conductors are disposed between the active areas and elongated in the second direction. Each one of the conductors has an overlap with at least one corresponding gate of the gates to form at least one capacitor.

公开(公告)号：US09748226B1

公开(公告)日：2017-08-29

申请号：US15055562

申请日：2016-02-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Hui Chen ,  Hao-Chieh Chan ,  Wei-Chih Chen

IPC: H01L27/06 ,  H01L49/02 ,  H01L27/02 ,  H01L23/528

CPC classification number: H01L27/0629 ,  H01L23/528 ,  H01L27/0207 ,  H01L28/40

Abstract: A device is disclosed that includes active areas, gates, and conductors. The active areas are disposed apart from each other. The gates are crossing over the active areas. The conductors are disposed over the active areas and disposed between the active areas. Each one of the conductors disposed between the active areas is arranged between adjacent two of the gates, and has an overlap with at least one corresponding gate of the gates to form at least one capacitor.

公开(公告)号：US10515947B2

公开(公告)日：2019-12-24

申请号：US16138785

申请日：2018-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Hui Chen ,  Hao-Chieh Chan ,  Wei-Chih Chen

IPC: H01L27/108 ,  H01L27/06 ,  H01L49/02 ,  H01L27/02 ,  H01L23/528

Abstract: A device includes a plurality of active areas, a plurality of gates, and a plurality of conductors. The active areas are elongated in a first direction. The gates are elongated in a second direction. The conductors are disposed between the active areas and elongated in the second direction. Each one of the conductors has an overlap with at least one corresponding gate of the gates to form at least one capacitor.

公开(公告)号：US10083955B2

公开(公告)日：2018-09-25

申请号：US15663644

申请日：2017-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Hui Chen ,  Hao-Chieh Chan ,  Wei-Chih Chen

IPC: H01L27/06 ,  H01L23/528 ,  H01L49/02 ,  H01L27/02

CPC classification number: H01L27/0629 ,  H01L23/5223 ,  H01L23/528 ,  H01L27/0207 ,  H01L28/40

Abstract: A device includes a plurality of active areas, a plurality of gates, and a plurality of conductors. The active areas are elongated in a first direction. The gates are elongated in a second direction. The conductors are disposed between the active areas and elongated in the second direction. Each one of the conductors has an overlap with at least one corresponding gate of the gates to form at least one capacitor.

公开(公告)号：US11817452B2

公开(公告)日：2023-11-14

申请号：US17227199

申请日：2021-04-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Hui Chen ,  Hao-Chieh Chan ,  Wei-Chih Chen

IPC: H01L29/94 ,  H01L27/06 ,  H01L49/02 ,  H01L27/02 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/0629 ,  H01L23/528 ,  H01L23/5223 ,  H01L27/0207 ,  H01L28/40

Abstract: A method disclosed includes the following operations as below: forming at least one capacitor between multiple interposing conductors and multiple gates; and forming multiple interposing connectors connected to the interposing conductors. One of the interposing conductors is interposed between two adjacent gates of the gates. In a plain view, the interposing connectors are separate from the gates.

公开(公告)号：US20220208957A1

公开(公告)日：2022-06-30

申请号：US17655431

申请日：2022-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Chieh Chan ,  Chung-Hui Chen

IPC: H01L49/02 ,  H01L23/522 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L27/08 ,  H01L27/06 ,  H01L29/94

Abstract: A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.