公开(公告)号：US20230121153A1

公开(公告)日：2023-04-20

申请号：US18069887

申请日：2022-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fong-Yuan CHANG ,  Kuo-Nan YANG ,  Chung-Hsing WANG ,  Lee-Chung LU ,  Sheng-Fong CHEN ,  Po-Hsiang HUANG ,  Hiranmay BISWAS ,  Sheng-Hsiung CHEN ,  Aftab Alam KHAN

IPC: H01L27/02 ,  H01L23/522 ,  H01L27/118 ,  G06F30/394

Abstract: An integrated circuit includes a cell layer including a first cell and a second cell, a first metal layer over the cell layer and having a first conductive feature, a second metal layer over the first metal layer and having a second conductive feature, and a first via between the first metal layer and the second metal layer and connecting the first conductive feature to the second conductive feature. The first conductive feature spans over a boundary between the first and second cells, and has a lengthwise direction along a first direction. The second conductive feature spans over the boundary between the first and second cells, and has a lengthwise direction along a second direction that is perpendicular to the first direction.

公开(公告)号：US20210217743A1

公开(公告)日：2021-07-15

申请号：US17214703

申请日：2021-03-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fong-Yuan CHANG ,  Kuo-Nan YANG ,  Chung-Hsing WANG ,  Lee-Chung LU ,  Sheng-Fong CHEN ,  Po-Hsiang HUANG ,  Hiranmay BISWAS ,  Sheng-Hsiung CHEN ,  Aftab Alam KHAN

IPC: H01L27/02 ,  H01L23/522 ,  H01L27/118 ,  G06F30/394

Abstract: A method includes forming a cell layer including first and second cells, each of which is configured to perform a circuit function; forming a first metal layer above the cell layer and including a first conductive feature and a second conductive feature extending along a first direction, in which the first conductive feature extends from the first cell into the second cell, and in which a shortest distance between a center line of the first conductive feature and a center line of the second conductive feature along a second direction is less than a width of the first conductive feature, and the second direction is perpendicular to the first direction; forming a first conductive via interconnecting the cell layer and the conductive feature.

公开(公告)号：US20200279812A1

公开(公告)日：2020-09-03

申请号：US16875060

申请日：2020-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hiranmay BISWAS ,  Kuo-Nan YANG ,  Chung-Hsing WANG

IPC: H01L23/528 ,  H01L23/50 ,  H01L23/522 ,  G06F30/392 ,  G06F30/394

Abstract: A power grid of an integrated circuit (IC) is provided. The power grid includes a plurality of first power lines formed in a first metal layer, a plurality of second power lines formed in the first metal layer, a plurality of third power lines formed in a second metal layer and a plurality of fourth power lines formed in the second metal layer. The second power lines are parallel to the first power lines, and the first and second power lines are interlaced in the first metal layer. The third power lines are perpendicular to the first power lines. The fourth power lines are parallel to the third power lines, and the third and fourth power lines are interlaced in the second metal layer. A first power pitch between two adjacent third power lines is greater than a second power pitch between two adjacent fourth power lines.

公开(公告)号：US20180166386A1

公开(公告)日：2018-06-14

申请号：US15651165

申请日：2017-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hiranmay BISWAS ,  Kuo-Nan YANG ,  Chung-Hsing WANG

IPC: H01L23/528 ,  G06F17/50 ,  H01L23/50

Abstract: A power grid of an integrated circuit (IC) is provided. The power grid includes a plurality of first power lines formed in a first metal layer, a plurality of second power lines formed in the first metal layer and parallel to the first power lines, a plurality of third power lines formed in a second metal layer, and a plurality of fourth power lines formed in the second metal layer and parallel to the third power lines. The first and second power lines are interlaced in the first metal layer. The third and fourth power lines are interlaced in the second metal layer. Distances from the individual first power line to the two adjacent second power lines are the same, and distances from the individual third power line to the two adjacent fourth power lines are different.

公开(公告)号：US20190148352A1

公开(公告)日：2019-05-16

申请号：US16122762

申请日：2018-09-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fong-Yuan CHANG ,  Kuo-Nan YANG ,  Chung-Hsing WANG ,  Lee-Chung LU ,  Sheng-Fong CHEN ,  Po-Hsiang HUANG ,  Hiranmay BISWAS ,  Sheng-Hsiung CHEN ,  Aftab Alam KHAN

IPC: H01L27/02 ,  G06F17/50 ,  H01L23/522

Abstract: An integrated circuit includes a cell layer, a first metal layer, and a first conductive via. The cell layer includes first and second cells, each of which is configured to perform a circuit function. The first metal layer is above the cell layer and includes a first conductive feature that extends from the first cell into the second cell and that is configured to receive a supply voltage. A first conductive via interconnects the cell layer and the metal layer.