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公开(公告)号：US20180144087A1
公开(公告)日：2018-05-24
申请号：US15355410
申请日：2016-11-18
发明人： Chin-Shen LIN , Ming-Hsien LIN , Kuo-Nan YANG , Chung-Hsing WANG
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036 , G06F17/5077
摘要： A FIT evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC comprising a number of metal lines and a number of VIAs; picking a number of nodes along the metal lines; dividing each of the metal lines into a number of metal segments based on the nodes; and determining a FIT value for each of the metal segments or VIAs to verify the layout and fabricate the IC.
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公开(公告)号：US20230121153A1
公开(公告)日：2023-04-20
申请号：US18069887
申请日：2022-12-21
发明人： Fong-Yuan CHANG , Kuo-Nan YANG , Chung-Hsing WANG , Lee-Chung LU , Sheng-Fong CHEN , Po-Hsiang HUANG , Hiranmay BISWAS , Sheng-Hsiung CHEN , Aftab Alam KHAN
IPC分类号： H01L27/02 , H01L23/522 , H01L27/118 , G06F30/394
摘要： An integrated circuit includes a cell layer including a first cell and a second cell, a first metal layer over the cell layer and having a first conductive feature, a second metal layer over the first metal layer and having a second conductive feature, and a first via between the first metal layer and the second metal layer and connecting the first conductive feature to the second conductive feature. The first conductive feature spans over a boundary between the first and second cells, and has a lengthwise direction along a first direction. The second conductive feature spans over the boundary between the first and second cells, and has a lengthwise direction along a second direction that is perpendicular to the first direction.
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公开(公告)号：US20210217743A1
公开(公告)日：2021-07-15
申请号：US17214703
申请日：2021-03-26
发明人： Fong-Yuan CHANG , Kuo-Nan YANG , Chung-Hsing WANG , Lee-Chung LU , Sheng-Fong CHEN , Po-Hsiang HUANG , Hiranmay BISWAS , Sheng-Hsiung CHEN , Aftab Alam KHAN
IPC分类号： H01L27/02 , H01L23/522 , H01L27/118 , G06F30/394
摘要： A method includes forming a cell layer including first and second cells, each of which is configured to perform a circuit function; forming a first metal layer above the cell layer and including a first conductive feature and a second conductive feature extending along a first direction, in which the first conductive feature extends from the first cell into the second cell, and in which a shortest distance between a center line of the first conductive feature and a center line of the second conductive feature along a second direction is less than a width of the first conductive feature, and the second direction is perpendicular to the first direction; forming a first conductive via interconnecting the cell layer and the conductive feature.
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公开(公告)号：US20160004809A1
公开(公告)日：2016-01-07
申请号：US14857212
申请日：2015-09-17
发明人： Chin-Shen LIN , Jerry Chang-Jui KAO , Nitesh KATTA , Chou-Kun LIN , Yi-Chuin TSAI , Chi-Yeh YU , Kuo-Nan YANG
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5077 , G06F2217/76 , G06F2217/78 , G06F2217/82 , H01L23/5226 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A method is disclosed that includes the operations outlined below. A first criteria is determined to be met when directions of a first current and a second current around a first end and a second end of a metal segment respectively are opposite, in which the metal segment is a part of a power rail in at least one design file of a semiconductor device and is enclosed by only two terminal via arrays. A second criteria is determined to be met when a length of the metal segment is not larger than a electromigration critical length. The metal segment is included in the semiconductor device with a first current density limit depending on the length of the metal segment when the first and the second criteria are met.
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公开(公告)号：US20150095864A1
公开(公告)日：2015-04-02
申请号：US14098435
申请日：2013-12-05
发明人： Chin-Shen LIN , Jerry Chang-Jui KAO , Nitesh KATTA , Chou-Kun LIN , Yi-Chuin TSAI , Chi-Yeh YU , Kuo-Nan YANG
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5077 , G06F2217/76 , G06F2217/78 , G06F2217/82 , H01L23/5226 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A method is disclosed that includes the operations outlined below. A first criteria is determined to be met when directions of a first current and a second current around a first end and a second end of a metal segment respectively are opposite, in which the metal segment is a part of a power rail in at least one design file of a semiconductor device and is enclosed by only two terminal via arrays. A second criteria is determined to be met when a length of the metal segment is not larger than a electromigration critical length. The metal segment is included in the semiconductor device with a first current density limit depending on the length of the metal segment when the first and the second criteria are met.
摘要翻译： 公开了一种包括以下概述的操作的方法。 当金属片段的第一端和第二端周围的第一电流和第二电流的方向分别相反时，第一标准被确定为满足，其中金属片段是至少一个中的电源轨的一部分 半导体器件的设计文件，仅由两个端子通孔阵列封装。 当金属段的长度不大于电迁移临界长度时，确定满足第二标准。 当符合第一和第二标准时，金属段被包括在半导体器件中，具有取决于金属段的长度的第一电流密度极限。
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公开(公告)号：US20190148352A1
公开(公告)日：2019-05-16
申请号：US16122762
申请日：2018-09-05
发明人： Fong-Yuan CHANG , Kuo-Nan YANG , Chung-Hsing WANG , Lee-Chung LU , Sheng-Fong CHEN , Po-Hsiang HUANG , Hiranmay BISWAS , Sheng-Hsiung CHEN , Aftab Alam KHAN
IPC分类号： H01L27/02 , G06F17/50 , H01L23/522
摘要： An integrated circuit includes a cell layer, a first metal layer, and a first conductive via. The cell layer includes first and second cells, each of which is configured to perform a circuit function. The first metal layer is above the cell layer and includes a first conductive feature that extends from the first cell into the second cell and that is configured to receive a supply voltage. A first conductive via interconnects the cell layer and the metal layer.
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公开(公告)号：US20210200930A1
公开(公告)日：2021-07-01
申请号：US17204275
申请日：2021-03-17
发明人： Chin-Shen LIN , Ming-Hsien LIN , Kuo-Nan YANG , Chung-Hsing WANG
IPC分类号： G06F30/398 , G06F30/394
摘要： A failure-in-time (FIT) evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC including a metal line and a plurality of vertical interconnect accesses (VIAs); picking a plurality of nodes along the metal line; dividing the metal line into a plurality of metal segments based on the nodes; and determining FIT value for each of the metal segments to verify the layout and fabricate the IC. The number of the nodes is less than the number of the VIAs, and a distance between two adjacent VIAs of the VIAs is less than a width of the metal line.
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公开(公告)号：US20200279812A1
公开(公告)日：2020-09-03
申请号：US16875060
申请日：2020-05-15
发明人： Hiranmay BISWAS , Kuo-Nan YANG , Chung-Hsing WANG
IPC分类号： H01L23/528 , H01L23/50 , H01L23/522 , G06F30/392 , G06F30/394
摘要： A power grid of an integrated circuit (IC) is provided. The power grid includes a plurality of first power lines formed in a first metal layer, a plurality of second power lines formed in the first metal layer, a plurality of third power lines formed in a second metal layer and a plurality of fourth power lines formed in the second metal layer. The second power lines are parallel to the first power lines, and the first and second power lines are interlaced in the first metal layer. The third power lines are perpendicular to the first power lines. The fourth power lines are parallel to the third power lines, and the third and fourth power lines are interlaced in the second metal layer. A first power pitch between two adjacent third power lines is greater than a second power pitch between two adjacent fourth power lines.
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公开(公告)号：US20190108306A1
公开(公告)日：2019-04-11
申请号：US16214243
申请日：2018-12-10
发明人： Chin-Shen LIN , Ming-Hsien LIN , Kuo-Nan YANG , Chung-Hsing WANG
IPC分类号： G06F17/50
摘要： A FIT evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC comprising a number of metal lines and a number of VIAs; picking a number of nodes along the metal lines; dividing each of the metal lines into a number of metal segments based on the nodes; and determining a FIT value for each of the metal segments or VIAs to verify the layout and fabricate the IC.
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公开(公告)号：US20180166386A1
公开(公告)日：2018-06-14
申请号：US15651165
申请日：2017-07-17
发明人： Hiranmay BISWAS , Kuo-Nan YANG , Chung-Hsing WANG
IPC分类号： H01L23/528 , G06F17/50 , H01L23/50
摘要： A power grid of an integrated circuit (IC) is provided. The power grid includes a plurality of first power lines formed in a first metal layer, a plurality of second power lines formed in the first metal layer and parallel to the first power lines, a plurality of third power lines formed in a second metal layer, and a plurality of fourth power lines formed in the second metal layer and parallel to the third power lines. The first and second power lines are interlaced in the first metal layer. The third and fourth power lines are interlaced in the second metal layer. Distances from the individual first power line to the two adjacent second power lines are the same, and distances from the individual third power line to the two adjacent fourth power lines are different.
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