公开(公告)号：US20240290865A1

公开(公告)日：2024-08-29

申请号：US18498697

申请日：2023-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  I-Hsin Yang

IPC: H01L29/66 ,  H01L27/06 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L27/0688 ,  H01L27/0922 ,  H01L29/0665 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7869

Abstract: An embodiment includes a method including forming a first conductive feature and a second conductive feature in a substrate. The method also includes forming a first complementary field-effect transistor (CFET) over the substrate, the forming including forming a first lower transistor including a first gate and a first source/drain region. The method also includes forming a first upper transistor including a second gate and a second source/drain region, the first upper transistor overlapping the first lower transistor. The method also includes forming a conductive via fuse connected to the first conductive feature and the second source/drain region.