公开(公告)号：US12237188B2

公开(公告)日：2025-02-25

申请号：US18183491

申请日：2023-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Cheng Lin ,  Y. Y. Peng ,  Jerry Wang ,  Kewei Zuo ,  Chien Rhone Wang

IPC: G05B19/19 ,  G03F7/00 ,  G05B13/02 ,  H01L21/67

Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.

公开(公告)号：US20200006102A1

公开(公告)日：2020-01-02

申请号：US16405702

申请日：2019-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Cheng Lin ,  Y.Y. Peng ,  Jerry Wang ,  Kewei Zuo ,  Chien Rhone Wang

IPC: H01L21/67 ,  G05B13/02 ,  G05B19/19 ,  G03F7/20

Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.

公开(公告)号：US10964566B2

公开(公告)日：2021-03-30

申请号：US16405702

申请日：2019-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Cheng Lin ,  Y.Y. Peng ,  Jerry Wang ,  Kewei Zuo ,  Chien Rhone Wang

IPC: G05B19/19 ,  H01L21/67 ,  G05B13/02 ,  G03F7/20

Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.

公开(公告)号：US11626304B2

公开(公告)日：2023-04-11

申请号：US17178929

申请日：2021-02-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Cheng Lin ,  Y. Y. Peng ,  Jerry Wang ,  Kewei Zuo ,  Chien Rhone Wang

IPC: G05B19/19 ,  H01L21/67 ,  G05B13/02 ,  G03F7/20

Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.