公开(公告)号：US11935950B2

公开(公告)日：2024-03-19

申请号：US17408846

申请日：2021-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yu Chen ,  Wan-Hua Huang ,  Jing-Ying Chen ,  Kuo-Ming Wu

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/45 ,  H01L29/49

CPC classification number: H01L29/7835 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/0653 ,  H01L29/1087 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665

Abstract: A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.

公开(公告)号：US20240186412A1

公开(公告)日：2024-06-06

申请号：US18441118

申请日：2024-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yu Chen ,  Wan-Hua Huang ,  Jing-Ying Chen ,  Kuo-Ming Wu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/7835 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/0653 ,  H01L29/1087 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665

Abstract: A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.

公开(公告)号：US11894362B2

公开(公告)日：2024-02-06

申请号：US17168295

申请日：2021-02-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Ying Chen

IPC: H01L27/02

CPC classification number: H01L27/0262

Abstract: An ESD protection device protects a circuit from TLPs between a first terminal and a second terminal. The device includes an NPN discharge structure and a PNP triggering device. The first terminal is coupled to the p-doped emitter and the n-doped base of the PNP triggering device and also the n-doped emitter of the NPN discharge structure. The second terminal is coupled to the n-doped collector of the NPN discharge structure. The p-doped collector of the PNP triggering device is coupled to the p-doped base of the NPN discharge structure. A TLP causes base-collector junction breakdown in the PNP triggering device, which results in a current through the PNP triggering device. That current is injected into the base of the NPN discharge structure, which results in a larger discharge current through the NPN discharge structure. The device provides high holding voltage ESD protection device with snapback.

公开(公告)号：US20220254772A1

公开(公告)日：2022-08-11

申请号：US17168295

申请日：2021-02-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Ying Chen

IPC: H01L27/02

Abstract: An ESD protection device protects a circuit from TLPs between a first terminal and a second terminal. The device includes an NPN discharge structure and a PNP triggering device. The first terminal is coupled to the p-doped emitter and the n-doped base of the PNP triggering device and also the n-doped emitter of the NPN discharge structure. The second terminal is coupled to the n-doped collector of the NPN discharge structure. The p-doped collector of the PNP triggering device is coupled to the p-doped base of the NPN discharge structure. A TLP causes base-collector junction breakdown in the PNP triggering device, which results in a current through the PNP triggering device. That current is injected into the base of the NPN discharge structure, which results in a larger discharge current through the NPN discharge structure. The device provides high holding voltage ESD protection device with snapback.

公开(公告)号：US20210384349A1

公开(公告)日：2021-12-09

申请号：US17408846

申请日：2021-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yu Chen ,  Wan-Hua Huang ,  Jing-Ying Chen ,  Kuo-Ming Wu

IPC: H01L29/78 ,  H01L29/66

Abstract: A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.