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    Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) with Step Oxide
    3.
    发明申请
    Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) with Step Oxide 审中-公开
    具有阶跃氧化物的金属氧化物半导体场效应晶体管（MOSFET）

    公开(公告)号：US20140264588A1

    公开(公告)日：2014-09-18

    申请号：US13863697

    申请日：2013-04-16

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

    Inventor： Po-Yu Chen ,  Wan-Hua Huang ,  Kuo-Ming Wu

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/7816 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/512 ,  H01L29/513 ,  H01L29/6656 ,  H01L29/66689 ,  H01L29/7833 ,  H01L29/7835

    Abstract: The present disclosure relates to a method of ultra-high voltage UHV device formation which utilizes a composite step oxide as a gate oxide to achieve isolation of the gate and drain-side spacer from the drain region. The thickness of the step gate oxide improves device breakdown voltage, and allows for the drain to be self-aligned to the gate, thus reducing device drift region and improves device on state resistance. The composite isolation layer comprises two or more dielectric layers which are formed through a series of deposition and etch steps including thermal oxidation and chemical vapor deposition. The composite isolation layer may then be etched to form a self-align structure which utilizes the spacers as hard mask to achieve a reduced device pitch relative to some prior art methods. A thicker gate oxide under one or both spacers can improve yield and high temperature operating life of the UHV device.

    Abstract translation: 本公开涉及一种利用复合步进氧化物作为栅极氧化物以实现栅极和漏极侧隔离物与漏极区隔离的超高压特高压器件形成方法。 步进栅极氧化物的厚度提高了器件击穿电压，并允许漏极与栅极自对准，从而减少器件漂移区域，并提高器件导通状态电阻。 复合隔离层包括通过包括热氧化和化学气相沉积在内的一系列沉积和蚀刻步骤形成的两个或多个电介质层。 然后可以蚀刻复合隔离层以形成自对准结构，其利用间隔物作为硬掩模以相对于一些现有技术方法实现减小的器件间距。 在一个或两个间隔物下面较厚的栅极氧化物可以提高UHV器件的产量和高温工作寿命。

    High Voltage Transistor Structure
    4.
    发明申请
    High Voltage Transistor Structure 有权

    公开(公告)号：US20210384349A1

    公开(公告)日：2021-12-09

    申请号：US17408846

    申请日：2021-08-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Po-Yu Chen ,  Wan-Hua Huang ,  Jing-Ying Chen ,  Kuo-Ming Wu

    IPC: H01L29/78 ,  H01L29/66

    Abstract: A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.

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