公开(公告)号：US11088086B2

公开(公告)日：2021-08-10

申请号：US16395385

申请日：2019-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun-Ting Chen ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Chih-Wei Wu

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31

Abstract: A method for forming a chip package structure is provided. The method includes bonding a first chip structure and a second chip structure to a surface of a substrate. The first chip structure and the second chip structure are spaced apart from each other. There is a first gap between the first chip structure and the second chip structure. The method includes removing a first portion of the first chip structure and a second portion of the second chip structure to form a trench partially in the first chip structure and the second chip structure and partially over the first gap. The method includes forming an anti-warpage bar in the trench. The anti-warpage bar is over the first chip structure, the second chip structure, and the first gap.

公开(公告)号：US20200006286A1

公开(公告)日：2020-01-02

申请号：US16151340

申请日：2018-10-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun-Ting Chen ,  Chih-Wei Wu ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/538 ,  H01L21/66 ,  H01L21/48 ,  H01L21/683

Abstract: A manufacturing method and a packaging process are provided. A package having a first die and a second die is provided. A circuit substrate having a first warpage level is provided. The package is mounted onto the circuit substrate and then heated under an elevated temperature to bond the package to the circuit substrate. The package heated under the elevated temperature is warped with a second warpage level, and the first warpage level is substantially in conformity with the second warpage level.