公开(公告)号：US11043426B2

公开(公告)日：2021-06-22

申请号：US16578357

申请日：2019-09-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui-Ting Yang ,  Chih-Ming Lai ,  Chun-Kuang Chen ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Meng-Hung Shen ,  Ru-Gun Liu ,  Wei-Cheng Lin

IPC: H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a plurality of gate structures over a substrate, and forming a plurality of source and drain regions along opposing sides of the plurality of gate structures. A plurality of middle-of-the-line (MOL) structures are formed at locations laterally interleaved between the plurality of gate structures. The plurality of MOL structures are redefined by getting rid of a part but not all of one or more of the plurality of MOL structures. Redefining the plurality of MOL structures results in a plurality of MOL active structures arranged over the plurality of source and drain regions at an irregular pitch.

公开(公告)号：US20200020588A1

公开(公告)日：2020-01-16

申请号：US16578357

申请日：2019-09-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui-Ting Yang ,  Chih-Ming Lai ,  Chun-Kuang Chen ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Meng-Hung Shen ,  Ru-Gun Liu ,  Wei-Cheng Lin

IPC: H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a plurality of gate structures over a substrate, and forming a plurality of source and drain regions along opposing sides of the plurality of gate structures. A plurality of middle-of-the-line (MOL) structures are formed at locations laterally interleaved between the plurality of gate structures. The plurality of MOL structures are redefined by getting rid of a part but not all of one or more of the plurality of MOL structures. Redefining the plurality of MOL structures results in a plurality of MOL active structures arranged over the plurality of source and drain regions at an irregular pitch.

公开(公告)号：US10276499B2

公开(公告)日：2019-04-30

申请号：US15714172

申请日：2017-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei Peng ,  Chih-Ming Lai ,  Chun-Kuang Chen ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Ru-Gun Liu ,  Yung-Sung Yen

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L49/02

Abstract: In some embodiments, the present disclosure relates to an integrated chip having a lower power rail continuously extending over a plurality of gate structures. A first set of connection pins straddle a first edge of the lower power rail, and a second set of connection pins straddle a second edge of the lower power rail, which is opposite the first edge. The first set of connection pins and the second set of connection pins are electrically coupled to the lower power rail. An upper power rail is over the lower power rail and is electrically coupled to the first set of connection pins and the second set of connection pins. The first set of connection pins are arranged at a first pitch and the second set of connection pins arranged with respect to the first set of connection pins at a second pitch less than the first pitch.

公开(公告)号：US10096522B2

公开(公告)日：2018-10-09

申请号：US15148274

申请日：2016-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui-Ting Yang ,  Chih-Ming Lai ,  Chun-Kuang Chen ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Meng-Hung Shen ,  Ru-Gun Liu ,  Wei-Cheng Lin

IPC: H01L21/82 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

Abstract: The present disclosure relates to a method of forming an integrated chip having middle-of-the-line (MOL) structures arranged at an irregular pitch, and an associated method of formation. In some embodiments, the integrated chip has a well region with a plurality of source/drain regions. A plurality of gate structures are arranged over the well region at a regular pitch. A plurality of middle-of-the-line (MOL) structures are laterally interleaved between some of the plurality of gate structures and are arranged over the well region at an irregular pitch having a first pitch that is larger than the regular pitch. Since the MOL structures have an irregular pitch with a first pitch that is larger than the regular pitch, one or more of the plurality of gate structures are spaced apart from a closest gate or MOL structure by a space that reduces parasitic capacitance.

公开(公告)号：US20180019207A1

公开(公告)日：2018-01-18

申请号：US15714172

申请日：2017-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei Peng ,  Chih-Ming Lai ,  Chun-Kuang Chen ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Ru-Gun Liu ,  Yung-Sung Yen

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L21/76816 ,  H01L21/76892 ,  H01L23/5226 ,  H01L23/528 ,  H01L28/00

Abstract: In some embodiments, the present disclosure relates to an integrated chip having a lower power rail continuously extending over a plurality of gate structures. A first set of connection pins straddle a first edge of the lower power rail, and a second set of connection pins straddle a second edge of the lower power rail, which is opposite the first edge. The first set of connection pins and the second set of connection pins are electrically coupled to the lower power rail. An upper power rail is over the lower power rail and is electrically coupled to the first set of connection pins and the second set of connection pins. The first set of connection pins are arranged at a first pitch and the second set of connection pins arranged with respect to the first set of connection pins at a second pitch less than the first pitch.

公开(公告)号：US20170323832A1

公开(公告)日：2017-11-09

申请号：US15148274

申请日：2016-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui-Ting Yang ,  Chih-Ming Lai ,  Chun-Kuang Chen ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Meng-Hung Shen ,  Ru-Gun Liu ,  Wei-Cheng Lin

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/423 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L21/823437 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/785

Abstract: The present disclosure relates to a method of forming an integrated chip having middle-of-the-line (MOL) structures arranged at an irregular pitch, and an associated method of formation. In some embodiments, the integrated chip has a well region with a plurality of source/drain regions. A plurality of gate structures are arranged over the well region at a regular pitch. A plurality of middle-of-the-line (MOL) structures are laterally interleaved between some of the plurality of gate structures and are arranged over the well region at an irregular pitch having a first pitch that is larger than the regular pitch. Since the MOL structures have an irregular pitch with a first pitch that is larger than the regular pitch, one or more of the plurality of gate structures are spaced apart from a closest gate or MOL structure by a space that reduces parasitic capacitance.

公开(公告)号：US20170317027A1

公开(公告)日：2017-11-02

申请号：US15143842

申请日：2016-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Liang Chen ,  Chih-Ming Lai ,  Charles Chew-Yuen Young ,  Chi-Yeh Yu ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Pin-Dai Sue ,  Ru-Gun Liu ,  Shi-Wei Peng ,  Wen-Hao Chen ,  Yung-Sung Yen ,  Chun-Kuang Chen

IPC: H01L23/528 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L23/5286 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/522 ,  H01L23/5222 ,  H01L27/0924

Abstract: The present disclosure relates to an integrated chip that uses a metal strap to improve performance and reduce electromigration by coupling a middle-end-of-the-line (MEOL) layer to a power rail. In some embodiments, the integrated chip has an active area with a plurality of source/drain regions. The active area contacts a MEOL structure extending in a first direction. A first metal wire extends in a second direction, which is perpendicular to the first direction, at a location overlying the MEOL structure. A metal strap extending in a first direction is arranged over the first metal wire. The metal strap is configured to connect the first metal line to a power rail (e.g., which may be held at a supply or ground voltage), which extends in the second direction. By connecting the MEOL structure to the power rail by way of a metal strap, parasitic capacitance and electromigration may be reduced.

公开(公告)号：US11532751B2

公开(公告)日：2022-12-20

申请号：US17068444

申请日：2020-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Hui-Ting Yang ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Shih-Wei Peng ,  Wei-Cheng Lin ,  Lei-Chun Chou

IPC: H01L29/78 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L27/088 ,  H01L29/66 ,  H01L29/417 ,  H01L21/74 ,  H01L23/538 ,  H01L21/3213 ,  H01L23/528 ,  H01L23/535

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

公开(公告)号：US11088092B2

公开(公告)日：2021-08-10

申请号：US16106395

申请日：2018-08-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kam-Tou Sio ,  Chih-Ming Lai ,  Chun-Kuang Chen ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Chi-Yeh Yu ,  Jiann-Tyng Tzeng ,  Ru-Gun Liu ,  Wen-Hao Chen

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/00 ,  H01L23/485 ,  H01L21/8234 ,  H01L23/532

Abstract: The present disclosure relates to a method of forming an integrated chip. The method may be performed by forming first and second source regions within a substrate. The first and second source regions are separated by a drain region along a first direction. First and second middle-end-of-the-line (MEOL) structures are formed over the substrate. The first and second MEOL structures have bottom surfaces that continually extend past edges of the first and second source regions, respectively, along a second direction perpendicular to the first direction. A power rail is formed that is electrically coupled to the first and second MEOL structures. The power rail has a first interconnect wire, a via rail on and in contact with the first interconnect wire, and a second interconnect wire on and in contact with the via rail. The via rail continuously extends along the first direction past the first and second MEOL structures.

公开(公告)号：US20180358309A1

公开(公告)日：2018-12-13

申请号：US16106395

申请日：2018-08-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kam-Tou Sio ,  Chih-Ming Lai ,  Chun-Kuang Chen ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Chi-Yeh Yu ,  Jiann-Tyng Tzeng ,  Ru-Gun Liu ,  Wen-Hao Chen

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/485 ,  H01L23/522 ,  H01L21/8234 ,  H01L23/532

CPC classification number: H01L23/564 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L23/5286 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295

Abstract: The present disclosure relates to a method of forming an integrated chip. The method may be performed by forming first and second source regions within a substrate. The first and second source regions are separated by a drain region along a first direction. First and second middle-end-of-the-line (MEOL) structures are formed over the substrate. The first and second MEOL structures have bottom surfaces that continually extend past edges of the first and second source regions, respectively, along a second direction perpendicular to the first direction. A power rail is formed that is electrically coupled to the first and second MEOL structures. The power rail has a first interconnect wire, a via rail on and in contact with the first interconnect wire, and a second interconnect wire on and in contact with the via rail. The via rail continuously extends along the first direction past the first and second MEOL structures.