公开(公告)号：US20250004383A1

公开(公告)日：2025-01-02

申请号：US18346113

申请日：2023-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kenji YAMAZOE ,  Chih-Shiang CHOU

IPC: G03F7/00 ,  G03F1/70 ,  H01L21/033

Abstract: A process for forming a photolithography mask includes generating a sub-resolution assist feature (SRAF) pattern from a blank mask layout based on a target layout. The SRAF pattern can be generated using an iterative process including finding the gradient of a cost function. A main pattern can be generated simultaneously with the SRAF pattern or after generation of the SRAF pattern.

公开(公告)号：US20220276567A1

公开(公告)日：2022-09-01

申请号：US17187351

申请日：2021-02-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kenneth Lik Kin HO ,  Chien-Jen LAI ,  Kenji YAMAZOE ,  Xin ZHOU ,  Danping PENG

IPC: G03F7/20

Abstract: A method of enhancing a layout pattern includes determining a vector transmission cross coefficient (vector-TCC) operator of an optical system of a lithographic system based on an illumination source of the optical system and an exit pupil of the optical system of the lithographic system. The method also includes performing an optical proximity correction (OPC) operation of a layout pattern of a photo mask to generate an OPC corrected layout pattern. The OPC operation uses the vector-TCC operator to determine a projected pattern of the layout pattern of the photo mask on a wafer. The method includes producing the OPC corrected layout pattern on a mask blank to create a photo mask.

公开(公告)号：US20210096475A1

公开(公告)日：2021-04-01

申请号：US17121542

申请日：2020-12-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shinn-Sheng YU ,  Ru-Gun LIU ,  Hsu-Ting HUANG ,  Kenji YAMAZOE ,  Minfeng CHEN ,  Shuo-Yen CHOU ,  Chin-Hsiang LIN

IPC: G03F7/20

Abstract: A method of manufacturing a semiconductor device includes dividing a number of dies along an x axis in a die matrix in each exposure field in an exposure field matrix delineated on the semiconductor substrate, wherein the x axis is parallel to one edge of a smallest rectangle enclosing the exposure field matrix. A number of dies is divided along a y axis in the die matrix, wherein the y axis is perpendicular to the x axis. Sequences SNx0, SNx1, SNx, SNxr, SNy0, SNy1, SNy, and SNyr are formed. p*(Nbx+1)−2 stepping operations are performed in a third direction and first sequence exposure/stepping/exposure operations and second sequence exposure/stepping/exposure operations are performed alternately between any two adjacent stepping operations as well as before a first stepping operation and after a last stepping operation. A distance of each stepping operation in order follows the sequence SNx.

公开(公告)号：US20200041915A1

公开(公告)日：2020-02-06

申请号：US16525510

申请日：2019-07-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shinn-Sheng YU ,  Ru-Gun LIU ,  Hsu-Ting HUANG ,  Kenji YAMAZOE ,  Minfeng CHEN ,  Shuo-Yen CHOU ,  Chin-Hsiang LIN

IPC: G03F7/20

Abstract: A method of manufacturing a semiconductor device includes dividing a number of dies along an x axis in a die matrix in each exposure field in an exposure field matrix delineated on the semiconductor substrate, wherein the x axis is parallel to one edge of a smallest rectangle enclosing the exposure field matrix. A number of dies is divided along a y axis in the die matrix, wherein the y axis is perpendicular to the x axis. Sequences SNx0, SNx1, SNx, SNxr, SNy0, SNy1, SNy, and SNyr are formed. p*(Nbx+1)−2 stepping operations are performed in a third direction and first sequence exposure/stepping/exposure operations and second sequence exposure/stepping/exposure operations are performed alternately between any two adjacent stepping operations as well as before a first stepping operation and after a last stepping operation. A distance of each stepping operation in order follows the sequence SNx.