公开(公告)号：US20220367677A1

公开(公告)日：2022-11-17

申请号：US17815181

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bwo-Ning CHEN ,  Xusheng WU ,  Chang-Miao LIU ,  Shih-Hao LIN

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/02 ,  H01L21/768 ,  H01L29/165

Abstract: A method includes forming a silicon liner over a semiconductor device, which includes a dummy gate structure disposed over a substrate and S/D features disposed adjacent to the dummy gate structure, where the dummy gate structure traverses a channel region between the S/D features. The method further includes forming an ILD layer over the silicon liner, which includes elemental silicon, introducing a dopant species to the ILD layer, and subsequently removing the dummy gate structure to form a gate trench. Thereafter, the method proceeds to performing a thermal treatment to the doped ILD layer, thereby oxidizing the silicon liner, and forming a metal gate stack in the gate trench and over the oxidized silicon liner.

公开(公告)号：US20220223606A1

公开(公告)日：2022-07-14

申请号：US17711448

申请日：2022-04-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Wen SU ,  Yu-Kuan LIN ,  Shih-Hao LIN ,  Lien-Jung HUNG ,  Ping-Wei WANG

IPC: H01L27/112 ,  H01L21/02 ,  H01L21/306 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

Abstract: A memory device includes a substrate, a first transistor and a second transistor, a first word line, a second word line, and a bit line. The first transistor and the second transistor are over the substrate and are electrically connected to each other, in which each of the first and second transistors includes first semiconductor layers and second semiconductor layers, a gate structure, and source/drain structures, in which the first semiconductor layers are in contact with the second semiconductor layers, and a width of the first semiconductor layers is narrower than a width of the second semiconductor layers. The first word line is electrically connected to the gate structure of the first transistor. The second word line is electrically connected to the gate structure of the second transistor. The bit line is electrically connected to a first one of the source/drain structures of the first transistor.

公开(公告)号：US20210312997A1

公开(公告)日：2021-10-07

申请号：US16837227

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Wen SU ,  Kian-Long LIM ,  Wen-Chun KENG ,  Chang-Ta YANG ,  Shih-Hao LIN

IPC: G11C17/18 ,  H01L27/112 ,  G11C7/18

Abstract: A semiconductor memory device includes a first word line formed over a first active region. In some embodiments, a first metal line is disposed over and perpendicular to the first word line, where the first metal line is electrically connected to the first word line using a first conductive via, and where the first conductive via is disposed over the first active region. In some examples, the semiconductor memory device further includes a second metal line and a third metal line both parallel to the first metal line and disposed on opposing sides of the first metal line, where the second metal line is electrically connected to a source/drain region of the first active region using a second conductive via, and where the third metal line is electrically connected to the source/drain region of the first active region using a third conductive via.

公开(公告)号：US20240379817A1

公开(公告)日：2024-11-14

申请号：US18779190

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bwo-Ning CHEN ,  Xusheng WU ,  Chang-Miao LIU ,  Shih-Hao LIN

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L29/06 ,  H01L29/165 ,  H01L29/78

Abstract: A semiconductor structure includes a p-type metal-oxide semiconductor (PMOS) region and an n-type metal-oxide semiconductor (NMOS) region, first source/drain (S/D) features in the PMOS region and second S/D features in the NMOS region, a first channel region connecting the first S/D features and a second channel region connecting the second S/D features, a first high-k metal gate stack (HKMG) over the first channel region and a second HKMG over the second channel region, first gate spacers on sidewalls of the first HKMG and second gate spacers on sidewalls of the second HKMG, a first etch-stop layer (ESL) on the first S/D features and the first gate spacers and a second ESL on the second S/D features and the second gate spacers, an oxide layer on the first ESL but not the second ESL, and an interlayer dielectric (ILD) layer on the oxide layer and the second ESL.

公开(公告)号：US20220359538A1

公开(公告)日：2022-11-10

申请号：US17874045

申请日：2022-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Wen SU ,  Chih-Chuan YANG ,  Shih-Hao LIN ,  Yu-Kuan LIN ,  Lien-Jung HUNG ,  Ping-Wei WANG

IPC: H01L27/11 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66

Abstract: A memory device includes a substrate, first semiconductor fin, second semiconductor fin, first gate structure, second gate structure, first gate spacer, and a second gate spacer. The first gate structure crosses the first semiconductor fin. The second gate structure crosses the second semiconductor fin, the first gate structure extending continuously from the second gate structure, in which in a top view of the memory device, a width of the first gate structure is greater than a width of the second gate structure. The first gate spacer is on a sidewall of the first gate structure. The second gate spacer extends continuously from the first gate spacer and on a sidewall of the second gate structure, in which in the top view of the memory device, a width of the first gate spacer is less than a width of the second gate spacer.

公开(公告)号：US20220102359A1

公开(公告)日：2022-03-31

申请号：US17035371

申请日：2020-09-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Wen SU ,  Chih-Chuan YANG ,  Shih-Hao LIN ,  Yu-Kuan LIN ,  Lien-Jung HUNG ,  Ping-Wei WANG

IPC: H01L27/11 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238

Abstract: A memory device includes a substrate, first semiconductor fin, second semiconductor fin, first gate structure, second gate structure, first gate spacer, and a second gate spacer. The first gate structure crosses the first semiconductor fin. The second gate structure crosses the second semiconductor fin, the first gate structure extending continuously from the second gate structure, in which in a top view of the memory device, a width of the first gate structure is greater than a width of the second gate structure. The first gate spacer is on a sidewall of the first gate structure. The second gate spacer extends continuously from the first gate spacer and on a sidewall of the second gate structure, in which in the top view of the memory device, a width of the first gate spacer is less than a width of the second gate spacer.

公开(公告)号：US20210391341A1

公开(公告)日：2021-12-16

申请号：US16900200

申请日：2020-06-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Wen SU ,  Yu-Kuan LIN ,  Shih-Hao LIN ,  Lien-Jung HUNG ,  Ping-Wei WANG

IPC: H01L27/112 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66

Abstract: A memory device includes a substrate, first semiconductor layers and second semiconductor layers alternately stacked over the substrate, a first gate structure and a second gate structure crossing the first semiconductor layers and the second semiconductor layers, a first via and a second via over the first gate structure and the second gate structure, and a first word line and a second word line over the first via and the second via. Along a lengthwise direction of the first and second gate structures, a width of the first semiconductor layers is narrower than a width of the second semiconductor layers.

公开(公告)号：US20240265985A1

公开(公告)日：2024-08-08

申请号：US18614180

申请日：2024-03-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Wen SU ,  Kian-Long LIM ,  Wen-Chun KENG ,  Chang-Ta YANG ,  Shih-Hao LIN

IPC: G11C17/18 ,  G11C7/18 ,  H10B20/00

CPC classification number: G11C17/18 ,  G11C7/18 ,  H10B20/00

Abstract: A semiconductor memory device includes a first word line formed over a first active region. In some embodiments, a first metal line is disposed over and perpendicular to the first word line, where the first metal line is electrically connected to the first word line using a first conductive via, and where the first conductive via is disposed over the first active region. In some examples, the semiconductor memory device further includes a second metal line and a third metal line both parallel to the first metal line and disposed on opposing sides of the first metal line, where the second metal line is electrically connected to a source/drain region of the first active region using a second conductive via, and where the third metal line is electrically connected to the source/drain region of the first active region using a third conductive via.

公开(公告)号：US20240215230A1

公开(公告)日：2024-06-27

申请号：US18596115

申请日：2024-03-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Wen SU ,  Yu-Kuan LIN ,  Shih-Hao LIN ,  Lien-Jung HUNG ,  Ping-Wei WANG

IPC: H10B20/20 ,  H01L21/02 ,  H01L21/306 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786 ,  H10B20/00

CPC classification number: H10B20/20 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/30604 ,  H01L21/823431 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78696 ,  H10B20/00

Abstract: A memory device includes a substrate, a first transistor and a second transistor, a first word line, a second word line, and a bit line. The first transistor and the second transistor are over the substrate and are electrically connected to each other, in which each of the first and second transistors includes first semiconductor layers and second semiconductor layers, a gate structure, and source/drain structures, in which the first semiconductor layers are in contact with the second semiconductor layers, and a width of the first semiconductor layers is narrower than a width of the second semiconductor layers. The first word line is electrically connected to the gate structure of the first transistor. The second word line is electrically connected to the gate structure of the second transistor. The bit line is electrically connected to a first one of the source/drain structures of the first transistor.

公开(公告)号：US20230354573A1

公开(公告)日：2023-11-02

申请号：US17731781

申请日：2022-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Chao-Yuan CHANG ,  Shih-Hao LIN ,  Chia-Hao PAO ,  Feng-Ming CHANG ,  Lien-Jung HUNG ,  Ping-Wei WANG

IPC: H01L27/11 ,  G06F30/392 ,  G06F30/398

CPC classification number: H01L27/1116 ,  H01L27/1108 ,  G06F30/392 ,  G06F30/398 ,  G06F30/3953

Abstract: The present disclosure describes a memory structure including a memory cell array. The memory cell array includes memory cells and first n-type wells extending in a first direction. The memory structure also includes a second n-type well formed in a peripheral region of the memory structure. The second n-type well extends in a second direction and is in contact with a first n-type well of the first n-type wells. The memory structure further includes a pick-up region formed in the second n-type well. The pick-up region is electrically coupled to the first n-type well of first n-type wells.