公开(公告)号：US12166071B2

公开(公告)日：2024-12-10

申请号：US17884849

申请日：2022-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ko-Cheng Liu ,  Ming-Shuan Li ,  Ming-Lung Cheng ,  Chang-Miao Liu

IPC: H01L29/06 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/092 ,  H01L29/66

Abstract: A semiconductor structure includes a power rail, a dielectric layer over the power rail, a first source/drain feature over the dielectric layer, a via structure extending through the dielectric layer and electrically connecting the first source/drain feature to the power rail, and two dielectric fins disposed on both sides of the first source/drain feature. Each of the dielectric fins includes two seal spacers, a dielectric bottom cover between bottom portions of the seal spacers, a dielectric top cover between top portions of the seal spacers, and an air gap surrounded by the seal spacers, the dielectric bottom cover, and the dielectric top cover.

公开(公告)号：US20210376071A1

公开(公告)日：2021-12-02

申请号：US17118262

申请日：2020-12-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ko-Cheng Liu ,  Ming-Shuan Li ,  Ming-Lung Cheng ,  Chang-Miao Liu

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/092 ,  H01L23/522 ,  H01L29/66

Abstract: A method includes providing a structure having two fins extending from a substrate and an isolation structure adjacent to lower portions of the fins; forming a cladding layer over the isolation structure and over top and sidewalls of the fins; recessing the isolation structure using the cladding layer as an etch mask to expose the substrate; after the recessing of the isolation structure, depositing a seal layer over the substrate, the isolation structure, and the cladding layer; forming a sacrificial plug over the seal layer and between the two fins; and depositing a dielectric top cover over the sacrificial plug and laterally between the two fins.

公开(公告)号：US20240379744A1

公开(公告)日：2024-11-14

申请号：US18780742

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ko-Cheng Liu ,  Ming-Shuan Li ,  Ming-Lung Cheng ,  Chang-Miao Liu

IPC: H01L29/06 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/092 ,  H01L29/66

Abstract: A semiconductor structure includes a power rail, a dielectric layer over the power rail, a first source/drain feature over the dielectric layer, a via structure extending through the dielectric layer and electrically connecting the first source/drain feature to the power rail, and two dielectric fins disposed on both sides of the first source/drain feature. Each of the dielectric fins includes two seal spacers, a dielectric bottom cover between bottom portions of the seal spacers, a dielectric top cover between top portions of the seal spacers, and an air gap surrounded by the seal spacers, the dielectric bottom cover, and the dielectric top cover.

公开(公告)号：US11600695B2

公开(公告)日：2023-03-07

申请号：US17118262

申请日：2020-12-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ko-Cheng Liu ,  Ming-Shuan Li ,  Ming-Lung Cheng ,  Chang-Miao Liu

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/092 ,  H01L23/522

Abstract: A method includes providing a structure having two fins extending from a substrate and an isolation structure adjacent to lower portions of the fins; forming a cladding layer over the isolation structure and over top and sidewalls of the fins; recessing the isolation structure using the cladding layer as an etch mask to expose the substrate; after the recessing of the isolation structure, depositing a seal layer over the substrate, the isolation structure, and the cladding layer; forming a sacrificial plug over the seal layer and between the two fins; and depositing a dielectric top cover over the sacrificial plug and laterally between the two fins.

公开(公告)号：US20220384570A1

公开(公告)日：2022-12-01

申请号：US17884849

申请日：2022-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ko-Cheng Liu ,  Ming-Shuan Li ,  Ming-Lung Cheng ,  Chang-Miao Liu

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/092 ,  H01L23/522

Abstract: A semiconductor structure includes a power rail, a dielectric layer over the power rail, a first source/drain feature over the dielectric layer, a via structure extending through the dielectric layer and electrically connecting the first source/drain feature to the power rail, and two dielectric fins disposed on both sides of the first source/drain feature. Each of the dielectric fins includes two seal spacers, a dielectric bottom cover between bottom portions of the seal spacers, a dielectric top cover between top portions of the seal spacers, and an air gap surrounded by the seal spacers, the dielectric bottom cover, and the dielectric top cover.