公开(公告)号：US20240379744A1

公开(公告)日：2024-11-14

申请号：US18780742

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ko-Cheng Liu ,  Ming-Shuan Li ,  Ming-Lung Cheng ,  Chang-Miao Liu

IPC: H01L29/06 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/092 ,  H01L29/66

Abstract: A semiconductor structure includes a power rail, a dielectric layer over the power rail, a first source/drain feature over the dielectric layer, a via structure extending through the dielectric layer and electrically connecting the first source/drain feature to the power rail, and two dielectric fins disposed on both sides of the first source/drain feature. Each of the dielectric fins includes two seal spacers, a dielectric bottom cover between bottom portions of the seal spacers, a dielectric top cover between top portions of the seal spacers, and an air gap surrounded by the seal spacers, the dielectric bottom cover, and the dielectric top cover.

公开(公告)号：US11600695B2

公开(公告)日：2023-03-07

申请号：US17118262

申请日：2020-12-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ko-Cheng Liu ,  Ming-Shuan Li ,  Ming-Lung Cheng ,  Chang-Miao Liu

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/092 ,  H01L23/522

Abstract: A method includes providing a structure having two fins extending from a substrate and an isolation structure adjacent to lower portions of the fins; forming a cladding layer over the isolation structure and over top and sidewalls of the fins; recessing the isolation structure using the cladding layer as an etch mask to expose the substrate; after the recessing of the isolation structure, depositing a seal layer over the substrate, the isolation structure, and the cladding layer; forming a sacrificial plug over the seal layer and between the two fins; and depositing a dielectric top cover over the sacrificial plug and laterally between the two fins.

公开(公告)号：US20220384570A1

公开(公告)日：2022-12-01

申请号：US17884849

申请日：2022-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ko-Cheng Liu ,  Ming-Shuan Li ,  Ming-Lung Cheng ,  Chang-Miao Liu

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/092 ,  H01L23/522

Abstract: A semiconductor structure includes a power rail, a dielectric layer over the power rail, a first source/drain feature over the dielectric layer, a via structure extending through the dielectric layer and electrically connecting the first source/drain feature to the power rail, and two dielectric fins disposed on both sides of the first source/drain feature. Each of the dielectric fins includes two seal spacers, a dielectric bottom cover between bottom portions of the seal spacers, a dielectric top cover between top portions of the seal spacers, and an air gap surrounded by the seal spacers, the dielectric bottom cover, and the dielectric top cover.

公开(公告)号：US12166071B2

公开(公告)日：2024-12-10

申请号：US17884849

申请日：2022-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ko-Cheng Liu ,  Ming-Shuan Li ,  Ming-Lung Cheng ,  Chang-Miao Liu

IPC: H01L29/06 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/092 ,  H01L29/66

Abstract: A semiconductor structure includes a power rail, a dielectric layer over the power rail, a first source/drain feature over the dielectric layer, a via structure extending through the dielectric layer and electrically connecting the first source/drain feature to the power rail, and two dielectric fins disposed on both sides of the first source/drain feature. Each of the dielectric fins includes two seal spacers, a dielectric bottom cover between bottom portions of the seal spacers, a dielectric top cover between top portions of the seal spacers, and an air gap surrounded by the seal spacers, the dielectric bottom cover, and the dielectric top cover.

公开(公告)号：US11810827B2

公开(公告)日：2023-11-07

申请号：US17338929

申请日：2021-06-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Lung Cheng ,  Yen-Chun Lin ,  Da-Wen Lin

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/823821 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/7843 ,  H01L29/7846 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/823892 ,  H01L27/0928

Abstract: A semiconductor device includes a P-type Field Effect Transistor (PFET) and an NFET. The PFET includes an N-well disposed in a substrate, a first fin structure disposed over the N-well, a first liner layer disposed over the N-well, and a second liner layer disposed over the first liner layer. The first liner layer and the second liner layer include different materials. The NFET includes a P-well disposed in the substrate, a second fin structure disposed over the P-well, a third liner layer disposed over the P-well. The third liner layer and the second liner layer include the same materials.

公开(公告)号：US11031299B2

公开(公告)日：2021-06-08

申请号：US16045992

申请日：2018-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Lung Cheng ,  Yen-Chun Lin ,  Da-Wen Lin

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/311

Abstract: A semiconductor device includes a P-type Field Effect Transistor (PFET) and an NFET. The PFET includes an N-well disposed in a substrate, a first fin structure disposed over the N-well, a first liner layer disposed over the N-well, and a second liner layer disposed over the first liner layer. The first liner layer and the second liner layer include different materials. The NFET includes a P-well disposed in the substrate, a second fin structure disposed over the P-well, a third liner layer disposed over the P-well. The third liner layer and the second liner layer include the same materials.

公开(公告)号：US10522417B2

公开(公告)日：2019-12-31

申请号：US15725544

申请日：2017-10-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Lung Cheng ,  Yen-Chun Lin ,  Da-Wen Lin

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311

Abstract: A semiconductor device includes a P-type Field Effect Transistor (PFET) and an NFET. The PFET includes an N-well disposed in a substrate, a first fin structure disposed over the N-well, a first liner layer disposed over the N-well, and a second liner layer disposed over the first liner layer. The first liner layer and the second liner layer include different materials. The NFET includes a P-well disposed in the substrate, a second fin structure disposed over the P-well, a third liner layer disposed over the P-well. The third liner layer and the second liner layer include the same materials.

公开(公告)号：US20180350697A1

公开(公告)日：2018-12-06

申请号：US16045992

申请日：2018-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Lung Cheng ,  Yen-Chun Lin ,  Da-Wen Lin

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L21/311 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0924 ,  H01L27/0928 ,  H01L29/7843

Abstract: A semiconductor device includes a P-type Field Effect Transistor (PFET) and an NFET. The PFET includes an N-well disposed in a substrate, a first fin structure disposed over the N-well, a first liner layer disposed over the N-well, and a second liner layer disposed over the first liner layer. The first liner layer and the second liner layer include different materials. The NFET includes a P-well disposed in the substrate, a second fin structure disposed over the P-well, a third liner layer disposed over the P-well. The third liner layer and the second liner layer include the same materials.

公开(公告)号：US20240395902A1

公开(公告)日：2024-11-28

申请号：US18791056

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Chih Lin ,  Yen-Ting Chen ,  Wen-Kai Lin ,  Szu-Chi Yang ,  Shih-Hao Lin ,  Tsung-Hung Lee ,  Ming-Lung Cheng

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.

公开(公告)号：US20210376071A1

公开(公告)日：2021-12-02

申请号：US17118262

申请日：2020-12-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ko-Cheng Liu ,  Ming-Shuan Li ,  Ming-Lung Cheng ,  Chang-Miao Liu

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/092 ,  H01L23/522 ,  H01L29/66

Abstract: A method includes providing a structure having two fins extending from a substrate and an isolation structure adjacent to lower portions of the fins; forming a cladding layer over the isolation structure and over top and sidewalls of the fins; recessing the isolation structure using the cladding layer as an etch mask to expose the substrate; after the recessing of the isolation structure, depositing a seal layer over the substrate, the isolation structure, and the cladding layer; forming a sacrificial plug over the seal layer and between the two fins; and depositing a dielectric top cover over the sacrificial plug and laterally between the two fins.