公开(公告)号：US20170062392A1

公开(公告)日：2017-03-02

申请号：US14840053

申请日：2015-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuang-Wei Cheng ,  Yi-Hsiu Chen ,  Ku-Feng Yang ,  Wen-Chih Chiou

IPC: H01L25/07 ,  H01L25/00 ,  H01L23/538

CPC classification number: H01L25/50 ,  H01L21/48 ,  H01L23/522 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/0657 ,  H01L2224/11 ,  H01L2225/06541 ,  H01L2225/06544

Abstract: Three dimensional integrated circuit structures and manufacturing methods of the same are disclosed. The three dimensional integrated circuit structure includes a first chip and a second chip. The first chip is bonded to the second chip at a bonding interface. A through via of the first chip and a bonding pad of the second chip are electrically connected, and a diffusion barrier layer of the through via contacts the bonding pad at the bonding interface.

Abstract translation: 公开了三维集成电路结构及其制造方法。 三维集成电路结构包括第一芯片和第二芯片。 第一芯片在接合界面处接合到第二芯片。 第一芯片的通孔和第二芯片的焊盘电连接，并且通孔的扩散阻挡层在接合界面处接触焊盘。

公开(公告)号：US09583465B1

公开(公告)日：2017-02-28

申请号：US14840053

申请日：2015-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuang-Wei Cheng ,  Yi-Hsiu Chen ,  Ku-Feng Yang ,  Wen-Chih Chiou

IPC: H01L23/00 ,  H01L25/07 ,  H01L23/538 ,  H01L25/00 ,  H01L21/48 ,  H01L23/522

CPC classification number: H01L25/50 ,  H01L21/48 ,  H01L23/522 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/0657 ,  H01L2224/11 ,  H01L2225/06541 ,  H01L2225/06544

Abstract: Three dimensional integrated circuit structures and manufacturing methods of the same are disclosed. The three dimensional integrated circuit structure includes a first chip and a second chip. The first chip is bonded to the second chip at a bonding interface. A through via of the first chip and a bonding pad of the second chip are electrically connected, and a diffusion barrier layer of the through via contacts the bonding pad at the bonding interface.

Abstract translation: 公开了三维集成电路结构及其制造方法。 三维集成电路结构包括第一芯片和第二芯片。 第一芯片在接合界面处接合到第二芯片。 第一芯片的通孔和第二芯片的焊盘电连接，并且通孔的扩散阻挡层在接合界面处接触焊盘。

公开(公告)号：US20240379505A1

公开(公告)日：2024-11-14

申请号：US18314356

申请日：2023-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Tsu Chung ,  Kuang-Wei Cheng ,  Yung-Chi Lin

IPC: H01L23/495 ,  H01L21/18 ,  H01L21/32 ,  H01L21/3213

Abstract: A method includes forming feature for a first package component, and the forming the feature includes a planarization process to level a top surface of the feature. A silicon-containing dielectric layer is deposited over and contacting the feature, and as a surface feature of the first package component. A second package component is bonded to the silicon-containing dielectric layer through fusion bonding. The silicon-containing dielectric layer has a same thickness in both steps of the depositing and the fusion bonding.