公开(公告)号：US20230343784A1

公开(公告)日：2023-10-26

申请号：US18343410

申请日：2023-06-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Guo-Huei WU ,  Po-Chun WANG ,  Hui-Zhong ZHUANG ,  Chih-Liang CHEN ,  Li-Chun TIEN

IPC: H01L27/092 ,  H01L23/538 ,  H01L29/06

CPC classification number: H01L27/092 ,  H01L23/5384 ,  H01L29/0649

Abstract: An integrated circuit is provided and includes first and second gates arranged in first and second layers, wherein the first and second gates extend in a first direction; a first insulating layer interposed between the first and second gates, wherein the first insulating layer, a first portion of the first gate, and a first portion of the second gate overlap with each other in a layout view; a cut layer, different from the first insulating layer, disposed on a second portion of the first gate; a first via passing through the cut layer and coupled to the second portion of the first gate; and a second via overlapping the first portion of the first gate and the first portion of the second gate, and coupled to the second gate. The first and second vias are configured to transmit different control signals to the first and second gates.

公开(公告)号：US20200328210A1

公开(公告)日：2020-10-15

申请号：US16806978

申请日：2020-03-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Guo-Huei WU ,  Po-Chun WANG ,  Hui-Zhong ZHUANG ,  Chih-Liang CHEN ,  Li-Chun TIEN

IPC: H01L27/092 ,  H01L23/538 ,  H01L29/06

Abstract: An integrated circuit includes a first transistor, a second transistor, and a first insulating layer. The first transistor is disposed in a first layer and comprises a first gate. The second transistor is disposed in a second layer above the first layer and comprises a second gate. The first gate and second gate are separated from each other in a first direction. The first insulating layer is disposed between the first gate of the first transistor and the second gate of the second transistor. The first insulating layer is configured to electrically insulate the first gate of the first transistor from the second gate of the second transistor.

公开(公告)号：US20190173456A1

公开(公告)日：2019-06-06

申请号：US16204932

申请日：2018-11-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ta-Pen GUO ,  Chi-Lin LIU ,  Shang-Chih HSIEH ,  Jerry Chang-Jui KAO ,  Li-Chun TIEN ,  Lee-Chung LU

IPC: H03K3/0233 ,  H01L27/02 ,  H03K3/01 ,  H03K19/094 ,  H03K23/58 ,  H03K3/356 ,  H01L27/118 ,  H03K3/3562

Abstract: A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.

公开(公告)号：US20180006009A1

公开(公告)日：2018-01-04

申请号：US15201200

申请日：2016-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Te LIN ,  Ting-Wei CHIANG ,  Hui-Zhong ZHUANG ,  Pin-Dai SUE ,  Li-Chun TIEN

IPC: H01L27/02 ,  G06F17/50 ,  H01L27/092

CPC classification number: H01L27/0207 ,  G06F17/5072 ,  G06F2217/02 ,  G06F2217/12 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L2027/11875

Abstract: An integrated circuit includes at least one first active region, at least one second active region adjacent to the first active region, and a plurality of third active regions. The first active region and the second active region are staggered. The third active regions are present adjacent to the first active region, wherein the third active regions are substantially aligned with each other.

公开(公告)号：US20240387504A1

公开(公告)日：2024-11-21

申请号：US18785842

申请日：2024-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Liang CHEN ,  Shun Li CHEN ,  Li-Chun TIEN ,  Ting Yu CHEN ,  Hui-Zhong ZHUANG

IPC: H01L27/02 ,  G06F30/392 ,  H01L27/092

Abstract: An integrated circuit (IC) device includes first to fourth circuits configured to perform corresponding functions. The first to fourth circuits correspondingly include first to fourth active regions extending along a first direction, and further include a plurality of gate regions extending along a second direction transverse to the first direction. Adjacent gate regions among the plurality of gate regions are spaced from each other along the first direction by one gate region pitch. The first active region and the second active region correspondingly have a first source/drain region and a second source/drain region spaced from each other, along the first direction, by one gate region pitch. The first source/drain region is a drain region. The plurality of gate regions includes a dummy gate region between the first source/drain region and the second source/drain region. The third active region and the fourth active region share a common source region.

公开(公告)号：US20240178215A1

公开(公告)日：2024-05-30

申请号：US18432543

申请日：2024-02-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  TSMC China Company Limited

Inventor： Xin-Yong WANG ,  Li-Chun TIEN ,  Chih-Liang CHEN

IPC: H01L27/02 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L27/0207 ,  H01L21/76816 ,  H01L23/5226

Abstract: An integrated circuit includes a first transistor, a second transistor, a first power line, and a second power line. The first transistor has a first active region and a first gate structure, in which the first active region has a source region and a drain region on opposite sides of the first gate structure. The second transistor is below the first transistor, and has a second active region and a second gate structure, in which the second active region has a source region and a drain region on opposite sides of the second gate structure. The first power line is above the first transistor, in which the first power line is electrically connected to the source region of first active region. The second power line is below the second transistor, in which the second power line is electrically connected to the source region of second active region.

公开(公告)号：US20220302111A1

公开(公告)日：2022-09-22

申请号：US17834752

申请日：2022-06-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Guo-Huei WU ,  Po-Chun WANG ,  Hui-Zhong ZHUANG ,  Chih-Liang CHEN ,  Li-Chun TIEN

IPC: H01L27/092 ,  H01L29/06 ,  H01L23/538

Abstract: A method is provided and includes operations below: forming a multilayer stack, wherein the multilayer stack includes multiple first semiconductor layers and multiple second semiconductor layers that are alternately stacked; forming a first source region and a first drain region on opposing sides of a first portion of the multilayer stack and forming a second source region and a second drain region on opposing sides of a second portion of the multilayer stack; removing the second semiconductor layers in the multilayer stack; forming a first gate region, corresponding to a first transistor, over the first portion of the multilayer stack; forming a first insulating layer above the first gate region; and forming a second gate region, corresponding to a second transistor, above the first insulating layer and over the second portion of the multilayer stack.

公开(公告)号：US20220157804A1

公开(公告)日：2022-05-19

申请号：US17108635

申请日：2020-12-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  TSMC China Company Limited

Inventor： Xin-Yong WANG ,  Li-Chun TIEN ,  Chih-Liang CHEN

IPC: H01L27/02 ,  H01L23/522 ,  H01L21/768

Abstract: An integrated circuit includes a first transistor, a second transistor, a first power line, and a second power line. The first transistor has a first active region and a first gate structure, in which the first active region has a source region and a drain region on opposite sides of the first gate structure. The second transistor is below the first transistor, and has a second active region and a second gate structure, in which the second active region has a source region and a drain region on opposite sides of the second gate structure. The first power line is above the first transistor, in which the first power line is electrically connected to the source region of first active region. The second power line is below the second transistor, in which the second power line is electrically connected to the source region of second active region.

公开(公告)号：US20210407986A1

公开(公告)日：2021-12-30

申请号：US16915954

申请日：2020-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shao-Lun CHIEN ,  Po-Chun WANG ,  Hui-Zhong ZHUANG ,  Chih-Liang CHEN ,  Li-Chun TIEN

IPC: H01L27/02 ,  H01L23/522 ,  G06F30/392

Abstract: An integrated circuit disclosed here includes several cell rows extending in a first direction and a multi-bit cell having several bit cells included in the cell rows. The bit cells include M bit cells, and an output signal of a N-th bit cell of the M bit cells is an input signal of a (N+1)-th bit cell of the M bit cells, N and M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell, and the N-th bit cell and the (N+1)-th bit cell are arranged diagonally in different cell rows in the multi-bit cell.

公开(公告)号：US20210384128A1

公开(公告)日：2021-12-09

申请号：US16909968

申请日：2020-06-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  TSMC NANJING COMPANY LIMITED ,  TSMC CHINA COMPANY LIMITED

Inventor： Xin-Yong WANG ,  Liu HAN ,  Li-Chun TIEN ,  Chih-Liang CHEN

IPC: H01L23/528 ,  H01L27/088 ,  H01L23/522 ,  H01L21/8234

Abstract: A device includes a transistor, an insulating structure, a buried conductive line, and a buried via. The transistor is above a substrate and includes a source/drain region and a source/drain contact above the source/drain region. The insulating structure is above the substrate and laterally surrounds the transistor. The buried conductive line is in the insulating structure and spaced apart from the transistor. The buried via is in the insulating structure and interconnects the transistor and the buried conductive line. A height of the buried conductive line is greater than a height of the source/drain contact.