公开(公告)号：US20200043921A1

公开(公告)日：2020-02-06

申请号：US16585683

申请日：2019-09-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Gerben DOORNBOS ,  Mark VAN DAL

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/8238

Abstract: In a method of manufacturing a semiconductor device, a fin structure protruding from a first isolation insulating layer is formed. A second isolation insulating layer made of different material than the first isolation insulating layer is formed so that a first upper portion of the fin structure is exposed. A dummy gate structure is formed over the exposed first upper portion of the first fin structure. The second isolation insulating layer is etched by using the dummy gate structure as an etching mask. The dummy gate structure is removed so that a gate space is formed. The second isolation insulating layer is etched in the gate space so that a second upper portion of the fin structure is exposed from the first isolation insulating layer. A gate dielectric layer and a gate electrode layer are formed over the exposed second portion of the fin structure.

公开(公告)号：US20190312107A1

公开(公告)日：2019-10-10

申请号：US16449611

申请日：2019-06-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Martin Christopher HOLLAND ,  Mark VAN DAL ,  Georgios VELLIANITIS ,  Blandine DURIEZ ,  Gerben DOORNBOS

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/04 ,  H01L29/165 ,  H01L29/775 ,  H01L29/417 ,  H01L29/78 ,  H01L29/40 ,  B82Y10/00

Abstract: A method includes forming a plurality of first semiconductor layers and second semiconductor layers in an alternate manner over a substrate; etching the first semiconductor layers and second semiconductor layers to form a fin structure, in which the fin structure comprises a plurality of first nanowires and second nanowires alternately arranged, the first nanowires have respective remaining portions of the first semiconductor layers, and the second nanowires have respective remaining portions of second semiconductor layers; forming a dummy gate over the fin structure; forming a plurality of gate spacers on opposite sidewalls of the dummy gate, respectively; replacing the dummy gate with a metal gate; removing first portions of the second nanowires exposed by the metal gate and metal gate and the gate spacers suspended; and forming an epitaxy layer wrapping around the first portions of the first nanowires, in which opposite sidewalls of the epitaxy layer have zig-zag contour.

公开(公告)号：US20190165134A1

公开(公告)日：2019-05-30

申请号：US16010425

申请日：2018-06-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Carlos H. DIAZ ,  Mark VAN DAL ,  Martin Christopher HOLLAND

IPC: H01L29/66 ,  H01L21/306 ,  H01L29/04 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor structure comprises etching a semiconductor substrate having a top surface extending along a (001) crystal plane, such that a majority of a top surface of the etched semiconductor substrate extends along {111} crystal planes; forming a first epitaxial layer in contact with the top surface of the etched semiconductor substrate; and forming a second epitaxial layer on the first epitaxial layer.

公开(公告)号：US20190148243A1

公开(公告)日：2019-05-16

申请号：US16201328

申请日：2018-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mark VAN DAL ,  Gerben DOORNBOS

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06

Abstract: A fin including a bottom portion, a first sacrificial layer disposed over the bottom portion, a first semiconductor layer disposed over the first sacrificial layer, a second sacrificial layer disposed over the first semiconductor layer and a second semiconductor layer disposed over the second sacrificial layer, is formed. The second semiconductor layer protrudes from a first insulating layer. A dummy gate is formed over the second semiconductor layer. A sidewall spacer layer is formed on side faces of the dummy gate. A first dielectric layer is formed over the dummy gate and the sidewall spacer layer. The dummy gate is removed, thereby forming a gate space. The first insulating layer is etched in the gate space, thereby exposing the first semiconductor layer and the first and second sacrificial layers. The first and second sacrificial layers are removed. A gate dielectric layer and a gate electrode layer are formed.

公开(公告)号：US20190131180A1

公开(公告)日：2019-05-02

申请号：US15798227

申请日：2017-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mark VAN DAL ,  Gerben Doornbos

IPC: H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a bottom portion, an intermediate portion disposed over the bottom portion and an upper portion disposed over the intermediate portion is formed. The intermediate portion is removed at a source/drain region of the fin structure, thereby forming a space between the bottom portion and the upper portion. An insulating layer is formed in the space. A source/drain contact layer is formed over the upper portion. The source/drain contact layer is separated by the insulating layer from the bottom portion of the fin structure.

公开(公告)号：US20180315817A1

公开(公告)日：2018-11-01

申请号：US15613339

申请日：2017-06-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mark VAN DAL ,  Gerben DOORNBOS ,  Chung-Te LIN

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a gate structure, at least one nanowire, at least one epitaxy structure, and at least one source/drain spacer. The gate structure is disposed on the substrate. The nanowire extends through the gate structure. The epitaxy structure is disposed on the substrate and is in contact with the nanowire. The source/drain spacer is disposed between the epitaxy structure and the gate structure and is embedded in the epitaxy structure.

公开(公告)号：US20210193532A1

公开(公告)日：2021-06-24

申请号：US17195441

申请日：2021-03-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mark VAN DAL ,  Gerben DOORNBOS

IPC: H01L21/8238 ,  H01L29/66 ,  H01L27/088 ,  H01L29/786 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8234

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a bottom portion, an intermediate portion disposed over the bottom portion and an upper portion disposed over the intermediate portion is formed. The intermediate portion is removed at a source/drain region of the fin structure, thereby forming a space between the bottom portion and the upper portion. An insulating layer is formed in the space. A source/drain contact layer is formed over the upper portion. The source/drain contact layer is separated by the insulating layer from the bottom portion of the fin structure.

公开(公告)号：US20210057547A1

公开(公告)日：2021-02-25

申请号：US17080613

申请日：2020-10-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Carlos H. DIAZ ,  Mark VAN DAL ,  Martin Christopher HOLLAND

IPC: H01L29/66 ,  H01L21/306 ,  H01L29/04 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78 ,  H01L21/308

Abstract: A semiconductor structure includes a substrate, a first epitaxial layer, a second epitaxial layer, and a transistor. The substrate includes a first pyramid protrusion, a second pyramid protrusion, a third pyramid protrusion, and a fourth pyramid protrusion. The first and second pyramid protrusions are arranged along a first direction, the second and fourth pyramid protrusions are arranged along the first direction, and the first and third pyramid protrusions are arranged along a second direction crossing the first direction. The first epitaxial layer is over the substrate and in contact with the first, second, third, and fourth pyramid protrusions. The second epitaxial layer is over the first epitaxial layer. The transistor is over the second epitaxial layer.

公开(公告)号：US20200219973A1

公开(公告)日：2020-07-09

申请号：US16826913

申请日：2020-03-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mark VAN DAL ,  Gerben DOORNBOS ,  Chung-Te LIN

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L27/06 ,  H01L21/8238 ,  H01L21/822 ,  H01L29/40 ,  H01L29/08 ,  H01L27/092 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/775 ,  H01L21/02

Abstract: Semiconductor structures and methods for forming the same are provided. The method includes forming a fin structure over a substrate, and the fin structure includes alternately stacked semiconductor material layers and sacrificial layers. The method further includes forming a dummy gate structure, recessing the fin structure to form an opening, forming first source/drain spacers on sidewalls of the sacrificial layers by performing a first atomic layer deposition (ALD) process, and forming source/drain structure in the opening. The method further includes removing the dummy gate structure and the sacrificial layers to expose the semiconductor material layers and forming a gate structure wrapping around the semiconductor material layers.

公开(公告)号：US20190131181A1

公开(公告)日：2019-05-02

申请号：US16201694

申请日：2018-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mark VAN DAL ,  Gerben DOORNBOS

IPC: H01L21/8238 ,  H01L29/66 ,  H01L27/088 ,  H01L29/786

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a bottom portion, an intermediate portion disposed over the bottom portion and an upper portion disposed over the intermediate portion is formed. The intermediate portion is removed at a source/drain region of the fin structure, thereby forming a space between the bottom portion and the upper portion. An insulating layer is formed in the space. A source/drain contact layer is formed over the upper portion. The source/drain contact layer is separated by the insulating layer from the bottom portion of the fin structure.