公开(公告)号：US10419005B2

公开(公告)日：2019-09-17

申请号：US15710506

申请日：2017-09-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ruey-Bin Shen ,  Tsung-Hsien Tsai ,  Chih-Hsien Chang

IPC分类号： H03L7/07 ,  H03L7/08 ,  H03L7/099 ,  H03L7/089 ,  H03L7/083 ,  H03L7/22

摘要： A phase-lock-loop (PLL) circuit includes a reference PLL circuit configured to generate a reference clock signal; a single clock tree circuit, coupled to the reference PLL circuit, and configured to distribute the reference clock signal; and a plurality of designated PLL circuits coupled to the clock tree circuit, wherein the designated PLL circuits are each configured to receive the distributed reference clock signal through the single clock tree circuit and provide a respective clock signal based on the reference clock signal.