公开(公告)号：US20250072050A1

公开(公告)日：2025-02-27

申请号：US18404533

申请日：2024-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wei HSU ,  Lung-Kun CHU ,  Jia-Ni YU ,  Chun-Fu LU ,  Shih-Hao LAI ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775

Abstract: An integrated circuit includes a transistor having a plurality of stacked channels each extending between the source/drain regions of the transistor. The transistor also includes a hard mask nanostructure above the highest channel and extending between the source/drain regions of the transistor. A gate dielectric and gate metals wrap around the channels and the hard mask nanostructure.