公开(公告)号：US20230040346A1

公开(公告)日：2023-02-09

申请号：US17701402

申请日：2022-03-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Pi CHANG ,  Huang-Lin CHAO ,  Chung-Liang CHENG ,  Pinyen LIN ,  Chun-Chun LIN ,  Tzu-Li LEE ,  Yu-Chia LIANG ,  Duen-Huei HOU ,  Wen-Chung LIU ,  Chun-I WU

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The semiconductor device includes a first gate structure and a second gate structure. The first gate structure includes a first interfacial oxide (IO) layer, a first high-K (HK) dielectric layer disposed on the first interfacial oxide layer, and a first dipole layer disposed at an interface between the first IL layer and the first HK dielectric layer. The HK dielectric layer includes a rare-earth metal dopant or an alkali metal dopant. The second gate structure includes a second IL layer, a second HK dielectric layer disposed on the second IL layer, and a second dipole layer disposed at an interface between the second IL layer and the second HK dielectric layer. The second HK dielectric layer includes a transition metal dopant and the rare-earth metal dopant or the alkali metal dopant.

公开(公告)号：US20220216165A1

公开(公告)日：2022-07-07

申请号：US17706039

申请日：2022-03-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jian-Hong LIN ,  Kuo-Yen LIU ,  Hsin-Chun CHANG ,  Tzu-Li LEE ,  Yu-Ching LEE ,  Yih-Ching WANG

IPC: H01L23/00 ,  H01L23/58 ,  H01L27/02 ,  H01L23/522

Abstract: An interconnect structure comprises a first dielectric layer, a first metal layer, a second dielectric layer, a metal via, and a second metal layer. The first dielectric layer is over a substrate. The first metal layer is over the first dielectric layer. The first metal layer comprises a first portion and a second portion spaced apart from the first portion. The second dielectric layer is over the first metal layer. The metal via has an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first metal layer, and a lower portion in the first dielectric layer. The second metal layer is over the metal via. From a top view the second metal layer comprises a metal line having longitudinal sides respectively set back from opposite sides of the first portion of the first metal layer.

公开(公告)号：US20240213180A1

公开(公告)日：2024-06-27

申请号：US18602392

申请日：2024-03-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jian-Hong LIN ,  Kuo-Yen LIU ,  Hsin-Chun CHANG ,  Tzu-Li LEE ,  Yu-Ching LEE ,  Yih-Ching WANG

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/58 ,  H01L27/02

CPC classification number: H01L23/562 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/585 ,  H01L27/0248 ,  H01L21/76805 ,  H01L2224/06519 ,  H01L2224/09519 ,  H01L2224/30519 ,  H01L2224/33519

Abstract: An interconnect structure includes a first dielectric layer, a first metal layer, a metal via, and a second metal layer. The first dielectric layer is over a substrate. The first metal layer is over the first dielectric layer and has a first segment and a second segment separated from the first segment. The metal via includes a first portion between the first and second segments of the first metal layer, and a second portion above the first metal layer. The second metal layer is over the metal via. From a top view, the second metal layer includes a metal line extending across the first and second segments of the first metal layer. From a cross-sectional view, the first portion of the metal via has opposite sidewalls respectively offset from opposite sidewalls of the second portion of the metal via.

公开(公告)号：US20140111781A1

公开(公告)日：2014-04-24

申请号：US13654750

申请日：2012-10-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shu-Hao CHANG ,  Tsiao-Chen WU ,  Chia-Hao HSU ,  Chia-Chen CHEN ,  Ying-Yu CHEN ,  Tzu-Li LEE ,  Shang-Chieh CHIEN ,  Jeng-Horng CHEN ,  Anthony YEN

IPC: G03F7/20

CPC classification number: G03F7/2002 ,  G03F7/20 ,  G03F7/70916 ,  G03F7/70933

Abstract: A method and apparatus for ultraviolet (UV) and extreme ultraviolet (EUV) lithography patterning is provided. A UV or EUV light beam is generated and directed to the surface of a substrate disposed on a stage and coated with photoresist. A laminar flow of a layer of inert gas is directed across and in close proximity to the substrate surface coated with photoresist during the exposure, i.e. lithography operation. The inert gas is exhausted quickly and includes a short resonance time at the exposure location. The inert gas flow prevents flue gasses and other contaminants produced by outgassing of the photoresist, to precipitate on and contaminate other features of the lithography apparatus.

Abstract translation: 提供了紫外线（UV）和极紫外（EUV）光刻图案的方法和装置。 产生UV或EUV光束并将其引导到设置在载物台上并涂覆有光致抗蚀剂的基板的表面。 惰性气体层的层流被引导穿过并且紧邻在曝光期间涂覆有光致抗蚀剂的基底表面，即光刻操作。 惰性气体迅速耗尽并且在曝光位置包括短的共振时间。 惰性气体流动防止烟气和其它由光致抗蚀剂脱气产生的污染物沉淀并污染光刻设备的其它特征。