公开(公告)号：US20170207298A1

公开(公告)日：2017-07-20

申请号：US14996235

申请日：2016-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Chang ,  Cheng-Yi Wu ,  Jian-Shin Tsai ,  Min-Hui Lin ,  Yi-Ming Lin ,  Chin-Szu Lee ,  Wen-Shan Chang ,  Yi-Hui Chen

IPC: H01L49/02

CPC classification number: H01L28/60

Abstract: Semiconductor devices and manufacturing method thereof are disclosed. The semiconductor device includes a substrate, a device layer, first and second conductive layers, first and second vias, and a MIM capacitor structure. The substrate includes active and passive regions. The device layer is in the active region. The first conductive layer is over the device layer. The second conductive layer is over the first conductive layer, wherein the first conductive layer is disposed between the device layer and the second conductive layer. The first via electrically connects the first and the second conductive layers. The MIM capacitor structure is between the first and the second conductive layers and in the passive region, and includes first and second electrodes and a capacitor dielectric layer therebetween. The capacitor dielectric layer includes Group IIIA-metal oxide or nitride. The second via electrically connects the second conductive layer and one of the first and second electrodes.

公开(公告)号：US10050102B2

公开(公告)日：2018-08-14

申请号：US14996235

申请日：2016-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Chang ,  Cheng-Yi Wu ,  Jian-Shin Tsai ,  Min-Hui Lin ,  Yi-Ming Lin ,  Chin-Szu Lee ,  Wen-Shan Chang ,  Yi-Hui Chen

IPC: H01L21/02 ,  H01L49/02

Abstract: Semiconductor devices and manufacturing method thereof are disclosed. The semiconductor device includes a substrate, a device layer, first and second conductive layers, first and second vias, and a MIM capacitor structure. The substrate includes active and passive regions. The device layer is in the active region. The first conductive layer is over the device layer. The second conductive layer is over the first conductive layer, wherein the first conductive layer is disposed between the device layer and the second conductive layer. The first via electrically connects the first and the second conductive layers. The MIM capacitor structure is between the first and the second conductive layers and in the passive region, and includes first and second electrodes and a capacitor dielectric layer therebetween. The capacitor dielectric layer includes Group IIIA-metal oxide or nitride. The second via electrically connects the second conductive layer and one of the first and second electrodes.