公开(公告)号：US20240297639A1

公开(公告)日：2024-09-05

申请号：US18646600

申请日：2024-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chia LAI ,  Meng-Hung SHEN ,  Chi-Lin LIU ,  Stefan RUSU ,  Yan-Hao CHEN ,  Jerry Chang-Jui KAO

IPC: H03K3/012 ,  H03K3/0233 ,  H03K3/037 ,  H03K3/289 ,  H03K3/356 ,  H03K3/3562

CPC classification number: H03K3/012 ,  H03K3/02332 ,  H03K3/0372 ,  H03K3/289 ,  H03K3/356104 ,  H03K3/3562 ,  H03K3/35625

Abstract: A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.

公开(公告)号：US20210175876A1

公开(公告)日：2021-06-10

申请号：US17180379

申请日：2021-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chia LAI ,  Meng-Hung SHEN ,  Chi-Lin LIU ,  Stefan RUSU ,  Yan-Hao CHEN ,  Jerry Chang-Jui KAO

IPC: H03K3/012 ,  H03K3/0233 ,  H03K3/289 ,  H03K3/037 ,  H03K3/3562 ,  H03K3/356

Abstract: A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.

公开(公告)号：US20190296719A1

公开(公告)日：2019-09-26

申请号：US16437541

申请日：2019-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chia LAI ,  Meng-Hung SHEN ,  Chi-Lin LIU ,  Stefan RUSU ,  Yan-Hao CHEN ,  Jerry Chang-Jui KAO

IPC: H03K3/012 ,  H03K3/289 ,  H03K3/3562 ,  H03K3/0233 ,  H03K3/356 ,  H03K3/037

Abstract: A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.