公开(公告)号：US20240297639A1

公开(公告)日：2024-09-05

申请号：US18646600

申请日：2024-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chia LAI ,  Meng-Hung SHEN ,  Chi-Lin LIU ,  Stefan RUSU ,  Yan-Hao CHEN ,  Jerry Chang-Jui KAO

IPC: H03K3/012 ,  H03K3/0233 ,  H03K3/037 ,  H03K3/289 ,  H03K3/356 ,  H03K3/3562

CPC classification number: H03K3/012 ,  H03K3/02332 ,  H03K3/0372 ,  H03K3/289 ,  H03K3/356104 ,  H03K3/3562 ,  H03K3/35625

Abstract: A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.

公开(公告)号：US20200313659A1

公开(公告)日：2020-10-01

申请号：US16900854

申请日：2020-06-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ta-Pen GUO ,  Chi-Lin LIU ,  Shang-Chih HSIEH ,  Jerry Chang-Jui KAO ,  Li-Chun TIEN ,  Lee-Chung LU

IPC: H03K3/0233 ,  H03K23/58 ,  H03K19/094 ,  H03K3/01 ,  H01L27/02 ,  H03K3/356 ,  H03K3/3562 ,  H01L27/118 ,  H01L27/092

Abstract: A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.

公开(公告)号：US20170170829A1

公开(公告)日：2017-06-15

申请号：US14968424

申请日：2015-12-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chi-Lin LIU ,  Lee-Chung LU ,  Shang-Chih HSIEH

IPC: H03K19/00 ,  H03K19/0948 ,  H03K19/20 ,  H03K3/037

CPC classification number: H03K19/0016 ,  H03K3/012 ,  H03K3/037 ,  H03K3/356121 ,  H03K19/0948 ,  H03K19/20

Abstract: A circuit is disclosed that includes a latch and a logic circuit. The latch includes is configured to generate a gating control signal in response to a latch enable signal and an input clock signal. The latch includes a pair of logic gates each configured to perform multi-level compound logic function. The logic circuit is configured to receive the gating control signal and the input clock signal, and generate an output clock signal in response to the gating control signal and the input clock signal.

公开(公告)号：US20230334208A1

公开(公告)日：2023-10-19

申请号：US18341545

申请日：2023-06-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheok-Kei LEI ,  Zhe-Wei JIANG ,  Chi-Yu LU ,  Yi-Hsin KO ,  Chi-Lin LIU ,  Hui-Zhong ZHUANG

IPC: G06F30/327 ,  H01L23/52 ,  H01L23/522 ,  G06F30/392 ,  G06F30/398

CPC classification number: G06F30/327 ,  H01L23/52 ,  H01L23/5222 ,  G06F30/392 ,  G06F30/398

Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in a layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.

公开(公告)号：US20210175876A1

公开(公告)日：2021-06-10

申请号：US17180379

申请日：2021-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chia LAI ,  Meng-Hung SHEN ,  Chi-Lin LIU ,  Stefan RUSU ,  Yan-Hao CHEN ,  Jerry Chang-Jui KAO

IPC: H03K3/012 ,  H03K3/0233 ,  H03K3/289 ,  H03K3/037 ,  H03K3/3562 ,  H03K3/356

Abstract: A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.

公开(公告)号：US20180183414A1

公开(公告)日：2018-06-28

申请号：US15841950

申请日：2017-12-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ta-Pen GUO ,  Chi-Lin LIU ,  Shang-Chih HSIEH ,  Jerry Chang-Jui KAO ,  Li-Chun TIEN ,  Lee-Chung LU

IPC: H03K3/0233 ,  H03K23/58 ,  H01L27/02 ,  H03K3/01 ,  H03K19/094

CPC classification number: H03K3/02332 ,  H01L27/0207 ,  H01L27/0233 ,  H01L27/11807 ,  H01L2027/11875 ,  H01L2027/11879 ,  H03K3/01 ,  H03K3/356121 ,  H03K3/35625 ,  H03K19/094 ,  H03K23/58

Abstract: A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.

公开(公告)号：US20200285792A1

公开(公告)日：2020-09-10

申请号：US16881706

申请日：2020-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheok-Kei LEI ,  Chi-Lin LIU ,  Hui-Zhong ZHUANG ,  Zhe-Wei JIANG ,  Chi-Yu LU ,  Yi-Hsin KO

IPC: G06F30/327 ,  H01L23/52 ,  H01L23/522 ,  G06F30/392 ,  G06F30/398

Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in an layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.

公开(公告)号：US20190296719A1

公开(公告)日：2019-09-26

申请号：US16437541

申请日：2019-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chia LAI ,  Meng-Hung SHEN ,  Chi-Lin LIU ,  Stefan RUSU ,  Yan-Hao CHEN ,  Jerry Chang-Jui KAO

IPC: H03K3/012 ,  H03K3/289 ,  H03K3/3562 ,  H03K3/0233 ,  H03K3/356 ,  H03K3/037

Abstract: A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.

公开(公告)号：US20190173456A1

公开(公告)日：2019-06-06

申请号：US16204932

申请日：2018-11-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ta-Pen GUO ,  Chi-Lin LIU ,  Shang-Chih HSIEH ,  Jerry Chang-Jui KAO ,  Li-Chun TIEN ,  Lee-Chung LU

IPC: H03K3/0233 ,  H01L27/02 ,  H03K3/01 ,  H03K19/094 ,  H03K23/58 ,  H03K3/356 ,  H01L27/118 ,  H03K3/3562

Abstract: A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.

公开(公告)号：US20150162910A1

公开(公告)日：2015-06-11

申请号：US14277896

申请日：2014-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Lin LIU ,  Shang-Chih HSIEH ,  Lee-Chung LU ,  Meng-Hsueh WANG ,  Chang-Yu WU

IPC: H03K19/00

CPC classification number: H03K19/0016 ,  H03K3/033 ,  H03K19/0013

Abstract: A circuit includes a clock trigger block and a logic circuit. The logic circuit is configured to output a signal to the clock trigger block based on a logic level of an enable signal received at the logic circuit. The clock trigger block is configured to output an output signal response to a clock signal received at the clock trigger block and the signal received from the logic circuit.

Abstract translation: 电路包括时钟触发块和逻辑电路。 逻辑电路被配置为基于在逻辑电路处接收的使能信号的逻辑电平将信号输出到时钟触发块。 时钟触发块被配置为输出对在时钟触发块处接收的时钟信号的输出信号响应和从逻辑电路接收的信号。