公开(公告)号：US20230378262A1

公开(公告)日：2023-11-23

申请号：US18364995

申请日：2023-08-03

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Shu-Han Chen ,  Yi-Shao Li ,  Chun-Heng Chen ,  Chi On Chui

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/0665 ,  H01L29/42364 ,  H01L29/785 ,  H01L29/42392 ,  H01L2029/7858

Abstract: A device includes a semiconductor nanostructure, and an oxide layer, which includes horizontal portions on a top surface and a bottom surface of the semiconductor nanostructure, vertical portions on sidewalls of the semiconductor nanostructure, and corner portions on corners of the semiconductor nanostructure. The horizontal portions have a first thickness. The vertical portions have a second thickness. The corner portions have a third thickness. Both of the second thickness and the third thickness are greater than the first thickness. A high-k dielectric layer surrounds the oxide layer. A gate electrode surrounds the high-k dielectric layer.

公开(公告)号：US12218197B2

公开(公告)日：2025-02-04

申请号：US18364995

申请日：2023-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Han Chen ,  Yi-Shao Li ,  Chun-Heng Chen ,  Chi On Chui

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: A device includes a semiconductor nanostructure, and an oxide layer, which includes horizontal portions on a top surface and a bottom surface of the semiconductor nanostructure, vertical portions on sidewalls of the semiconductor nanostructure, and corner portions on corners of the semiconductor nanostructure. The horizontal portions have a first thickness. The vertical portions have a second thickness. The corner portions have a third thickness. Both of the second thickness and the third thickness are greater than the first thickness. A high-k dielectric layer surrounds the oxide layer. A gate electrode surrounds the high-k dielectric layer.

公开(公告)号：US20230138136A1

公开(公告)日：2023-05-04

申请号：US17717839

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Shao Li ,  Shu-Han Chen ,  Chun-Heng Chen ,  Chi On Chui

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234

Abstract: A method of forming a nanostructure field-effect transistor (nano-FET) device includes: forming a fin structure that includes a fin and alternating layers of a first semiconductor material and a second semiconductor material overlying the fin; forming a dummy gate structure over the fin structure; forming source/drain regions over the fin structure on opposing sides of the dummy gate structure; removing the dummy gate structure to expose the first and second semiconductor materials under the dummy gate structure; selectively removing the exposed first semiconductor material, where after the selectively removing, the exposed second semiconductor material remains to form nanostructures, where different surfaces of the nanostructures have different atomic densities of the second semiconductor material; forming a gate dielectric layer around the nanostructures, thicknesses of the gate dielectric layer on the different surfaces of the nanostructures being formed substantially the same; and forming a gate electrode around the gate dielectric layer.

公开(公告)号：US20220102494A1

公开(公告)日：2022-03-31

申请号：US17369452

申请日：2021-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Han Chen ,  Yi-Shao Li ,  Chun-Heng Chen ,  Chi On Chui

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: A device includes a semiconductor nanostructure, and an oxide layer, which includes horizontal portions on a top surface and a bottom surface of the semiconductor nanostructure, vertical portions on sidewalls of the semiconductor nanostructure, and corner portions on corners of the semiconductor nanostructure. The horizontal portions have a first thickness. The vertical portions have a second thickness. The corner portions have a third thickness. Both of the second thickness and the third thickness are greater than the first thickness. A high-k dielectric layer surrounds the oxide layer. A gate electrode surrounds the high-k dielectric layer.

公开(公告)号：US20250142900A1

公开(公告)日：2025-05-01

申请号：US19003044

申请日：2024-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Han Chen ,  Yi-Shao Li ,  Chun-Heng Chen ,  Chi On Chui

IPC: H10D62/10 ,  H10D30/62 ,  H10D30/67 ,  H10D64/27

Abstract: A device includes a semiconductor nanostructure, and an oxide layer, which includes horizontal portions on a top surface and a bottom surface of the semiconductor nanostructure, vertical portions on sidewalls of the semiconductor nanostructure, and corner portions on corners of the semiconductor nanostructure. The horizontal portions have a first thickness. The vertical portions have a second thickness. The corner portions have a third thickness. Both of the second thickness and the third thickness are greater than the first thickness. A high-k dielectric layer surrounds the oxide layer. A gate electrode surrounds the high-k dielectric layer.

公开(公告)号：US11855140B2

公开(公告)日：2023-12-26

申请号：US17369452

申请日：2021-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Han Chen ,  Yi-Shao Li ,  Chun-Heng Chen ,  Chi On Chui

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/0665 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/785 ,  H01L2029/7858

Abstract: A device includes a semiconductor nanostructure, and an oxide layer, which includes horizontal portions on a top surface and a bottom surface of the semiconductor nanostructure, vertical portions on sidewalls of the semiconductor nanostructure, and corner portions on corners of the semiconductor nanostructure. The horizontal portions have a first thickness. The vertical portions have a second thickness. The corner portions have a third thickness. Both of the second thickness and the third thickness are greater than the first thickness. A high-k dielectric layer surrounds the oxide layer. A gate electrode surrounds the high-k dielectric layer.