公开(公告)号：US20240379364A1

公开(公告)日：2024-11-14

申请号：US18779365

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Jiun Peng ,  Hsiu-Hao Tsao ,  Shu-Han Chen ,  Chang-Jhih Syu ,  Kuo-Feng Yu ,  Jian-Hao Chen ,  Chih-Hao Yu ,  Chang-Yun Chang

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.

公开(公告)号：US20240145250A1

公开(公告)日：2024-05-02

申请号：US18411197

申请日：2024-01-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Han Chen ,  Tsung-Ju Chen ,  Ta-Hsiang Kung ,  Xiong-Fei Yu ,  Chi On Chui

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/28141 ,  H01L21/0234 ,  H01L21/28518 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/823456 ,  H01L21/823468 ,  H01L29/0847 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/45 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7856

Abstract: A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.

公开(公告)号：US20230126442A1

公开(公告)日：2023-04-27

申请号：US17662532

申请日：2022-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Ju Chen ,  Shu-Han Chen ,  Chun-Heng Chen ,  Chi On Chui

IPC: H01L29/66

Abstract: A method includes forming a dummy gate oxide on a wafer, and the dummy gate oxide is formed on a sidewall and a top surface of a protruding semiconductor fin in the wafer. The formation of the dummy gate oxide may include a Plasma Enhanced Chemical Vapor Deposition (PECVD) process in a deposition chamber, and the PECVD process includes applying a Radio Frequency (RF) power to a conductive plate below the wafer. The method further includes forming a dummy gate electrode over the dummy gate oxide, removing the dummy gate electrode and the dummy gate oxide to form a trench between opposing gate spacers, and forming a replacement gate in the trench.

公开(公告)号：US20220351975A1

公开(公告)日：2022-11-03

申请号：US17863006

申请日：2022-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Jiun Peng ,  Hsiu-Hao Tsao ,  Shu-Han Chen ,  Chang-Jhih Syu ,  Kuo-Feng Yu ,  Jian-Hao Chen ,  Chih-Hao Yu ,  Chang-Yun Chang

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/08 ,  H01L29/49 ,  H01L29/45 ,  H01L29/66 ,  H01L21/285 ,  H01L21/3115 ,  H01L21/311 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/02

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.

公开(公告)号：US10365672B2

公开(公告)日：2019-07-30

申请号：US15434201

申请日：2017-02-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shu-Han Chen ,  Sheng-Hung Lin ,  Han-Hsuan Hsu ,  Chien-Fang Lin

IPC: G06F19/00 ,  G05D23/19 ,  H01L21/67

Abstract: A system includes a cooling device, a memory, and a processor. The cooling device is configured to detect a temperature of a wafer and to provide air to the wafer. The memory is configured to store computer program codes. The processor is configured to execute the computer program codes in the memory to: determine whether the temperature of the wafer meet a predetermined requirement; adjust the temperature of the wafer on condition that the temperature does not meet the predetermined requirement; and control the cooling device to detect the temperature of the wafer again, in order to verify whether an adjusted temperature of the wafer meet predetermined requirement.

公开(公告)号：US20230378262A1

公开(公告)日：2023-11-23

申请号：US18364995

申请日：2023-08-03

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Shu-Han Chen ,  Yi-Shao Li ,  Chun-Heng Chen ,  Chi On Chui

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/0665 ,  H01L29/42364 ,  H01L29/785 ,  H01L29/42392 ,  H01L2029/7858

Abstract: A device includes a semiconductor nanostructure, and an oxide layer, which includes horizontal portions on a top surface and a bottom surface of the semiconductor nanostructure, vertical portions on sidewalls of the semiconductor nanostructure, and corner portions on corners of the semiconductor nanostructure. The horizontal portions have a first thickness. The vertical portions have a second thickness. The corner portions have a third thickness. Both of the second thickness and the third thickness are greater than the first thickness. A high-k dielectric layer surrounds the oxide layer. A gate electrode surrounds the high-k dielectric layer.

公开(公告)号：US20250142900A1

公开(公告)日：2025-05-01

申请号：US19003044

申请日：2024-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Han Chen ,  Yi-Shao Li ,  Chun-Heng Chen ,  Chi On Chui

IPC: H10D62/10 ,  H10D30/62 ,  H10D30/67 ,  H10D64/27

Abstract: A device includes a semiconductor nanostructure, and an oxide layer, which includes horizontal portions on a top surface and a bottom surface of the semiconductor nanostructure, vertical portions on sidewalls of the semiconductor nanostructure, and corner portions on corners of the semiconductor nanostructure. The horizontal portions have a first thickness. The vertical portions have a second thickness. The corner portions have a third thickness. Both of the second thickness and the third thickness are greater than the first thickness. A high-k dielectric layer surrounds the oxide layer. A gate electrode surrounds the high-k dielectric layer.

公开(公告)号：US20250048703A1

公开(公告)日：2025-02-06

申请号：US18490363

申请日：2023-10-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yu Wei ,  Hao-Ming Tang ,  Cheng-I Lin ,  Shu-Han Chen ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Semiconductor devices and methods of manufacture are presented. In embodiments a method of manufacturing the semiconductor device includes forming a fin from a plurality of semiconductor materials, depositing a dummy gate over the fin, depositing a plurality of spacers adjacent to the dummy gate, removing the dummy gate to form an opening adjacent to the plurality of spacers, widening the opening adjacent to a top surface of the plurality of spacers, after the widening, removing one of the plurality of semiconductor materials to form nanowires, and depositing a gate electrode around the nanowires.

公开(公告)号：US20250022879A1

公开(公告)日：2025-01-16

申请号：US18351099

申请日：2023-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Jui Chiu ,  Te-Yang Lai ,  An Lee ,  Jyun-Yi Wu ,  Shu-Han Chen ,  Da-Yuan Lee ,  Chi On Chui

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/775

Abstract: A method includes forming a first semiconductor channel region and a second semiconductor channel region, with the second semiconductor channel region overlapping the first semiconductor channel region, forming a first gate dielectric on the first semiconductor channel region, and forming a second gate dielectric on the second semiconductor channel region. A dipole dopant is incorporated into a first one of the first gate dielectric and the second gate dielectric to a higher atomic percentage, and a second one of the first gate dielectric and the second gate dielectric has a lower atomic percentage of the dipole dopant. A gate electrode is formed on both of the first gate dielectric and the second gate dielectric. The gate electrode and the first gate dielectric form parts of a first transistor, and the gate electrode and the second gate dielectric form parts of a second transistor.

公开(公告)号：US11855140B2

公开(公告)日：2023-12-26

申请号：US17369452

申请日：2021-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Han Chen ,  Yi-Shao Li ,  Chun-Heng Chen ,  Chi On Chui

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/0665 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/785 ,  H01L2029/7858

Abstract: A device includes a semiconductor nanostructure, and an oxide layer, which includes horizontal portions on a top surface and a bottom surface of the semiconductor nanostructure, vertical portions on sidewalls of the semiconductor nanostructure, and corner portions on corners of the semiconductor nanostructure. The horizontal portions have a first thickness. The vertical portions have a second thickness. The corner portions have a third thickness. Both of the second thickness and the third thickness are greater than the first thickness. A high-k dielectric layer surrounds the oxide layer. A gate electrode surrounds the high-k dielectric layer.