公开(公告)号：US12302557B2

公开(公告)日：2025-05-13

申请号：US18362092

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui ,  Chun-Chieh Lu ,  Yu-Ming Lin

IPC: G11C7/18 ,  G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: In an embodiment, a method includes forming a multi-layer stack including alternating layers of an isolation material and a semiconductor material, patterning the multi-layer stack to form a first channel structure in a first region of the multi-layer stack, where the first channel structure includes the semiconductor material, depositing a memory film layer over the first channel structure, etching a first trench extending through a second region of the multi-layer stack to form a first dummy bit line and a first dummy source line in the second region, where the first dummy bit line and first dummy source line each include the semiconductor material, and replacing the semiconductor material of the first dummy bit line and the first dummy source line with a conductive material to form a first bit line and a first source line.

公开(公告)号：US20250142932A1

公开(公告)日：2025-05-01

申请号：US19009221

申请日：2025-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H10D64/23 ,  H10D30/01 ,  H10D62/17 ,  H10D64/01 ,  H10D64/27 ,  H10D64/68 ,  H10D84/01 ,  H10D84/03 ,  H10D84/83 ,  H10D84/85

Abstract: Methods for forming contacts to source/drain regions and gate electrodes in low- and high-voltage devices and devices formed by the same are disclosed. In an embodiment a device includes a first channel region in a substrate adjacent a first source/drain region; a first gate over the first channel region; a second channel region in the substrate adjacent a second source/drain region, a top surface of the second channel region being below a top surface of the first channel region; a second gate over the second channel region; an ILD over the first gate and the second gate; a first contact extending through the ILD and coupled to the first source/drain region; and a second contact extending through the ILD, coupled to the second source/drain region, and having a width greater a width of the first contact and a height greater than a height of the first contact.

公开(公告)号：US12278287B2

公开(公告)日：2025-04-15

申请号：US18175346

申请日：2023-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Ziwei Fang ,  Chi On Chui ,  Huang-Lin Chao

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66

Abstract: The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.

公开(公告)号：US20250089313A1

公开(公告)日：2025-03-13

申请号：US18463466

申请日：2023-09-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Fong Tsai ,  Han-De Chen ,  Chi On Chui

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/04 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A method includes: epitaxially growing a first multi-layer stack over a first substrate; epitaxially growing a second multi-layer stack over a second substrate; and bonding the first multi-layer stack to the second multi-layer stack. The first substrate and the second substrate have different crystalline orientations. The method further includes patterning the first multi-layer stack and the second multi-layer stack to form a fin, the fin comprising a plurality of lower nanostructures alternatingly stacked with first dummy nanostructures and a plurality of upper nanostructures alternatingly stacked with second dummy nanostructure; replacing the first dummy nanostructures with a first gate stack, the first gate stack surrounding each of the plurality of lower nanostructures; and replacing the second dummy nanostructures with a second gate stack, the second gate stack surrounding each of the plurality of upper nanostructures.

公开(公告)号：US12237399B2

公开(公告)日：2025-02-25

申请号：US17458672

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-En Cheng ,  Yung-Cheng Lu ,  Chi On Chui ,  Wei-Yang Lee

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A method of forming a semiconductor device includes forming a sacrificial layer over a first stack of nanostructures and an isolation region. A dummy gate structure is formed over the first stack of nanostructures, and a first portion of the sacrificial layer. A second portion of the sacrificial layer is removed to expose a sidewall of the first stack of nanostructures adjacent the dummy gate structure. A spacer layer is formed over the dummy gate structure. A first portion of the spacer layer physically contacts the first stack of nanostructures.

公开(公告)号：US12218221B2

公开(公告)日：2025-02-04

申请号：US17744061

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Fang-Yi Liao ,  Shu Ling Liao ,  Yen-Chun Huang ,  Che-Hao Chang ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L21/44 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: Semiconductor devices including fin-shaped isolation structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a fin extending from a semiconductor substrate; a shallow trench isolation (STI) region over the semiconductor substrate adjacent the fin; and a dielectric fin structure over the STI region, the dielectric fin structure extending in a direction parallel to the fin, the dielectric fin structure including a first liner layer in contact with the STI region; and a first fill material over the first liner layer, the first fill material including a seam disposed in a lower portion of the first fill material and separated from a top surface of the first fill material, a first carbon concentration in the lower portion of the first fill material being greater than a second carbon concentration in an upper portion of the first fill material.

公开(公告)号：US12218199B2

公开(公告)日：2025-02-04

申请号：US18333981

申请日：2023-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Jia-Ming Lin ,  Chi On Chui

IPC: H01L29/06 ,  H01L21/265 ,  H01L27/092

Abstract: In an embodiment, a device includes: a first nanostructure; a second nanostructure; a gate dielectric around the first nanostructure and the second nanostructure, the gate dielectric including dielectric materials; and a gate electrode including: a work function tuning layer on the gate dielectric, the work function tuning layer including a pure work function metal, the pure work function metal of the work function tuning layer and the dielectric materials of the gate dielectric completely filling a region between the first nanostructure and the second nanostructure, the pure work function metal having a composition of greater than 95 at. % metals; an adhesion layer on the work function tuning layer; and a fill layer on the adhesion layer.

公开(公告)号：US12207478B2

公开(公告)日：2025-01-21

申请号：US17238678

申请日：2021-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chenchen Jacob Wang ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Chi On Chui

IPC: H10B61/00 ,  H01L21/02 ,  H01L29/24 ,  H10N50/01

Abstract: In an embodiment, a semiconductor device includes a first dielectric layer over a substrate and a first access transistor and a second access transistor in a memory cell of a memory array, the first access transistor and the second access transistor each including a bottom electrode in the first dielectric layer, a conductive gate in a second dielectric layer, where the second dielectric layer is over the bottom electrode and the first dielectric layer, a channel region extending through the conductive gate to contact the bottom electrode, and a top electrode over the channel region.

公开(公告)号：US12199158B2

公开(公告)日：2025-01-14

申请号：US18178644

申请日：2023-03-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Ho Lin ,  Chun-Heng Chen ,  Xiong-Fei Yu ,  Chi On Chui

IPC: H01L21/76 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes forming a fin protruding over a substrate; forming a conformal oxide layer over an upper surface and along sidewalls of the fin; performing an anisotropic oxide deposition or an anisotropic plasma treatment to form a non-conformal oxide layer over the upper surface and along the sidewalls of the fin; and forming a gate electrode over the fin, the conformal oxide layer and the non-conformal oxide layer being between the fin and the gate electrode.

公开(公告)号：US12166074B2

公开(公告)日：2024-12-10

申请号：US17651869

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Hsiang-Pi Chang ,  Huang-Lin Chao ,  Chung-Liang Cheng ,  Chi On Chui ,  Kun-Yu Lee ,  Tzer-Min Shen ,  Yen-Tien Tung ,  Chun-I Wu

IPC: H01L21/00 ,  H01L21/324 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.