公开(公告)号：US09349785B2

公开(公告)日：2016-05-24

申请号：US14091643

申请日：2013-11-27

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Yu-Jen Chen ,  Ping-Pang Hsieh ,  Hsin-Chi Chen

IPC: H01L21/8222 ,  H01L21/20 ,  H01L49/02 ,  H01L21/762 ,  H01L27/08 ,  H01L21/265

CPC classification number: H01L27/0802 ,  H01L21/2652 ,  H01L21/76224 ,  H01L28/20 ,  H01L29/0649

Abstract: A semiconductor device includes a semiconductor substrate, trench isolations, a sacrificial layer, a first resist protect oxide (RPO) layer, a second RPO layer and a silicide layer. The semiconductor substrate has first portions and second portions which are alternately disposed, and each of the second portions includes a first resist region with a first resistance, a second resist region with a second resistance and a silicide region. The second resistance is greater than the first resistance. The trench isolations are in the first portions. The sacrificial layer is on the first resist region. The first RPO layer is on the sacrificial layer. The first RPO layer together with the sacrificial layer have a first thickness. The second RPO layer is on the second resist region, in which the second RPO layer has a second thickness smaller than the first thickness. The silicide layer is on the silicide region.

Abstract translation: 半导体器件包括半导体衬底，沟槽隔离，牺牲层，第一抗蚀保护氧化物（RPO）层，第二RPO层和硅化物层。 半导体衬底具有交替设置的第一部分和第二部分，并且每个第二部分包括具有第一电阻的第一抗蚀剂区域，具有第二电阻的第二抗蚀剂区域和硅化物区域。 第二阻力大于第一阻力。 沟槽隔离处于第一部分。 牺牲层位于第一抗蚀剂区域上。 第一个RPO层在牺牲层上。 第一RPO层与牺牲层一起具有第一厚度。 第二RPO层位于第二抗蚀剂区域上，其中第二RPO层具有小于第一厚度的第二厚度。 硅化物层位于硅化物区域上。

公开(公告)号：US20150145099A1

公开(公告)日：2015-05-28

申请号：US14091643

申请日：2013-11-27

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Yu-Jen Chen ,  Ping-Pang Hsieh ,  Hsin-Chi Chen

IPC: H01L49/02 ,  H01L21/762 ,  H01L21/265 ,  H01L29/06

CPC classification number: H01L27/0802 ,  H01L21/2652 ,  H01L21/76224 ,  H01L28/20 ,  H01L29/0649

Abstract: A semiconductor device includes a semiconductor substrate, trench isolations, a sacrificial layer, a first resist protect oxide (RPO) layer, a second RPO layer and a silicide layer. The semiconductor substrate has first portions and second portions which are alternately disposed, and each of the second portions includes a first resist region with a first resistance, a second resist region with a second resistance and a silicide region. The second resistance is greater than the first resistance. The trench isolations are in the first portions. The sacrificial layer is on the first resist region. The first RPO layer is on the sacrificial layer. The first RPO layer together with the sacrificial layer have a first thickness. The second RPO layer is on the second resist region, in which the second RPO layer has a second thickness smaller than the first thickness. The silicide layer is on the silicide region.

Abstract translation: 半导体器件包括半导体衬底，沟槽隔离，牺牲层，第一抗蚀保护氧化物（RPO）层，第二RPO层和硅化物层。 半导体衬底具有交替设置的第一部分和第二部分，并且每个第二部分包括具有第一电阻的第一抗蚀剂区域，具有第二电阻的第二抗蚀剂区域和硅化物区域。 第二阻力大于第一阻力。 沟槽隔离处于第一部分。 牺牲层位于第一抗蚀剂区域上。 第一个RPO层在牺牲层上。 第一RPO层与牺牲层一起具有第一厚度。 第二RPO层位于第二抗蚀剂区域上，其中第二RPO层具有小于第一厚度的第二厚度。 硅化物层位于硅化物区域上。

公开(公告)号：US10181425B1

公开(公告)日：2019-01-15

申请号：US15651749

申请日：2017-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chan-Yu Hung ,  Ling-Sung Wang ,  Yu-Jen Chen ,  I-Shan Huang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/423 ,  H01L29/49 ,  H01L21/3065 ,  H01L21/027 ,  H01L21/308

Abstract: Semiconductor device structures with reduced gate end width formed at gate structures and methods for manufacturing the same are provided. In one example, a semiconductor device structure includes a plurality of gate structures formed over a plurality of fin structures, the gate structures formed substantially orthogonal to the fin structures, wherein the plurality of gate structures includes a first gate structure having a first gate end width and a second gate structure having a second gate end width, wherein the second gate end width is shorter than the first gate end width.