公开(公告)号：US20250118679A1

公开(公告)日：2025-04-10

申请号：US18483657

申请日：2023-10-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsiung PENG ,  Shih-Chi FU ,  Kuei-Shun CHEN ,  Yu-Lun LIU

IPC: H01L23/544 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/8234

Abstract: A method includes: forming a first mask over a substrate; forming first openings and a second opening in the first mask; forming first wells in first regions of the substrate exposed by the first openings and an alignment implant in a second region of the substrate exposed by the second opening; forming an alignment mark by recessing the alignment implant; and patterning a multi-layer semiconductor lattice under alignment of the alignment mark.