公开(公告)号：US20250118679A1

公开(公告)日：2025-04-10

申请号：US18483657

申请日：2023-10-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsiung PENG ,  Shih-Chi FU ,  Kuei-Shun CHEN ,  Yu-Lun LIU

IPC: H01L23/544 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/8234

Abstract: A method includes: forming a first mask over a substrate; forming first openings and a second opening in the first mask; forming first wells in first regions of the substrate exposed by the first openings and an alignment implant in a second region of the substrate exposed by the second opening; forming an alignment mark by recessing the alignment implant; and patterning a multi-layer semiconductor lattice under alignment of the alignment mark.

公开(公告)号：US20240395813A1

公开(公告)日：2024-11-28

申请号：US18498334

申请日：2023-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsiung PENG ,  Shih-Chi FU ,  Kuei-Shun CHEN ,  Te-Yu CHEN

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A method includes: forming a first stack of semiconductor channels and a second stack of semiconductor channels over a substrate, the first stack being adjacent the second stack, a transition region overlapping neighboring protruding corners of the first stack and the second stack; forming a plurality of sacrificial gates over the first stack and the second stack, the plurality of sacrificial gates extending in a first direction and being arranged along a second direction transverse the first direction based on a first pitch along a second direction, each of the plurality of sacrificial gates having a first width; simultaneously with the forming a plurality of sacrificial gates, forming a bar structure over the transition region and adjacent to the plurality of sacrificial gates, the bar structure having a second width that exceeds a sum of the first pitch and the first width; forming a plurality of source/drain openings in areas of the first and second stacks of semiconductor channels that are exposed by the plurality of sacrificial gates and the bar structure; forming a plurality of source/drain regions in the plurality of source/drain openings; replacing the plurality of sacrificial gates with a plurality of gate structures that wrap around the semiconductor channels of the first and second stacks; simultaneously with replacing the plurality of sacrificial gates, replacing the bar structure with an inactive gate structure; and replacing the inactive gate structure with an isolation structure.