公开(公告)号：US11935830B2

公开(公告)日：2024-03-19

申请号：US17446515

申请日：2021-08-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Te-Hsin Chiu ,  Shih-Wei Peng ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng ,  Jiun-Wei Lu

IPC分类号： H01L23/528 ,  H01L21/38 ,  H01L21/768

CPC分类号： H01L23/528 ,  H01L21/38 ,  H01L21/768

摘要： An integrated circuit includes multiple backside conductive layers disposed over a backside of a substrate. The multiple backside conductive layers each includes conductive segments. The conductive segments in at least one of the backside conductive layers are configured to transmit one or more power signals. The conductive segments of the multiple backside conductive layers cover select areas of the backside of the substrate, thereby leaving other areas of the backside of the substrate exposed.

公开(公告)号：US11437998B2

公开(公告)日：2022-09-06

申请号：US17186256

申请日：2021-02-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Kam-Tou Sio ,  Jiun-Wei Lu

IPC分类号： H03K19/17736 ,  H03K19/17784 ,  G06F1/10

摘要： An integrated circuit is disclosed, including a first latch circuit, a second latch circuit, and a clock circuit. The first latch circuit transmits multiple data signals to the second latch circuit through multiple first conductive lines disposed on a front side of the integrated circuit. The clock circuit transmits a first clock signal and a second clock signal to the first latch circuit and the second latch circuit through multiple second conductive lines disposed on a backside, opposite of the front side, of the integrated circuit.

公开(公告)号：US11909396B2

公开(公告)日：2024-02-20

申请号：US17872490

申请日：2022-07-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Kam-Tou Sio ,  Jiun-Wei Lu

IPC分类号： H03K19/17736 ,  G06F1/10 ,  H03K19/17784

CPC分类号： H03K19/1774 ,  G06F1/10 ,  H03K19/17784

摘要： An integrated circuit is provided, including a first latch circuit, a second latch circuit, and a clock circuit. The first latch circuit transmits multiple data signals to the second latch circuit through multiple first conductive lines disposed on a front side of the integrated circuit. The clock circuit transmits a first clock signal and a second clock signal to the first latch circuit and the second latch circuit through multiple second conductive lines disposed on a backside, opposite of the front side, of the integrated circuit.