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公开(公告)号：US20120262441A1
公开(公告)日：2012-10-18
申请号：US13437038
申请日：2012-04-02
IPC分类号： G09G5/00
CPC分类号： G09G3/3677 , G09G2310/0205 , G09G2310/08
摘要： A display device includes a driving circuit that applies an active potential which is a potential for turning on pixel transistors sequentially to a plurality of output signal lines, wherein the driving circuit includes a main driving circuit that outputs the active potential to one end of the output signal line of the plurality of output signal lines by applying a clock signal caused by a input of the active potential output from the upper output signal line, and an auxiliary driving circuit that has an auxiliary transistor which is a transistor where the other end of the output signal line is connected to a signal line for the clock signal via the source or the drain. Thereby, output waveform distortion in the scanning signal line can be improved and thus display quality can be enhanced.
摘要翻译： 显示装置包括：驱动电路，其施加作为使像素晶体管顺序地接通到多个输出信号线的电位的有效电位，其中，所述驱动电路包括将所述有源电位输出到所述输出的一端的主驱动电路 通过施加由从上部输出信号线输出的有效电位的输入引起的时钟信号，以及具有作为晶体管的辅助晶体管的辅助晶体管的多个输出信号线的信号线， 输出信号线通过源极或漏极连接到时钟信号的信号线。 由此，能够提高扫描信号线的输出波形失真，能够提高显示质量。
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公开(公告)号：US08912992B2
公开(公告)日：2014-12-16
申请号：US13437038
申请日：2012-04-02
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G2310/0205 , G09G2310/08
摘要： A display device includes a driving circuit that applies an active potential which is a potential for turning on pixel transistors sequentially to a plurality of output signal lines, wherein the driving circuit includes a main driving circuit that outputs the active potential to one end of the output signal line of the plurality of output signal lines by applying a clock signal caused by a input of the active potential output from the upper output signal line, and an auxiliary driving circuit that has an auxiliary transistor which is a transistor where the other end of the output signal line is connected to a signal line for the clock signal via the source or the drain. Thereby, output waveform distortion in the scanning signal line can be improved and thus display quality can be enhanced.
摘要翻译： 显示装置包括：驱动电路，其施加作为使像素晶体管顺序地接通到多个输出信号线的电位的有效电位，其中，所述驱动电路包括将所述有源电位输出到所述输出的一端的主驱动电路 通过施加由从上部输出信号线输出的有效电位的输入引起的时钟信号，以及具有作为晶体管的辅助晶体管的辅助晶体管的多个输出信号线的信号线， 输出信号线通过源极或漏极连接到时钟信号的信号线。 由此，能够提高扫描信号线的输出波形失真，能够提高显示质量。
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公开(公告)号：US20120280967A1
公开(公告)日：2012-11-08
申请号：US13460890
申请日：2012-05-01
申请人： Motoharu Miyamoto , Takahiro Ochiai
发明人： Motoharu Miyamoto , Takahiro Ochiai
IPC分类号： G09G5/00
CPC分类号： G11C19/28 , G09G3/3677 , G09G2300/0434 , G09G2310/0286
摘要： Provided is a gate signal line drive circuit including a shift register basic circuit for applying a high voltage for a signal high period and a low voltage for a signal low period to a gate signal line at the time of a screen display. The shift register basic circuit includes a gate line high voltage applying circuit applying a high voltage for the signal high period to the gate signal line, and a gate line low voltage applying circuit applying a low voltage to the gate signal line, wherein in the shift register basic circuit, the off-voltage is applied to the switch of the gate line low voltage applying circuit for a predetermined period at the time of a screen non-display.
摘要翻译： 提供了一种栅极信号线驱动电路，其包括用于在屏幕显示时向门信号线施加用于信号高电平的高电压和用于信号低电平的低电压的移位寄存器基本电路。 移位寄存器基本电路包括向栅极信号线施加用于信号高周期的高电压的栅极线高压施加电路和向栅极信号线施加低电压的栅极线路低压施加电路，其中， 寄存器基本电路，在屏幕不显示时，将预失真电压施加到栅极线路低压施加电路的开关一段预定时间。
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公开(公告)号：US20130057525A1
公开(公告)日：2013-03-07
申请号：US13604775
申请日：2012-09-06
申请人： Motoharu Miyamoto , Takahiro Ochiai
发明人： Motoharu Miyamoto , Takahiro Ochiai
IPC分类号： G06F3/038
CPC分类号： G09G3/3677 , G09G2310/0281
摘要： In a driving circuit, one output circuit has a scanning signal line, a first transistor which controls electrical connection between the scanning signal line and a clock signal line which has a gate connected to a first node, the first node which is at an active potential in a first time period including a time period during which the active potential is output to the scanning signal line, a second transistor which electrically connects the first node and an inactive signal line which has a potential to open the transistor in a second time period other than the first time period, and the second transistor has a gate connected to a second node, wherein the second node has two kinds of timings to be charged for retaining the active potential.
摘要翻译： 在驱动电路中，一个输出电路具有扫描信号线，第一晶体管控制扫描信号线与连接到第一节点的栅极的时钟信号线之间的电连接，第一节点处于有效电位 在包括有效电位输出到扫描信号线的时间段的第一时间段中，将第一晶体管和第二晶体管电连接的第二晶体管，第二晶体管在第二时间段内具有电位以打开晶体管的其他 并且第二晶体管具有连接到第二节点的栅极，其中第二节点具有用于保持有效电位而被充电的两种定时。
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公开(公告)号：US08907882B2
公开(公告)日：2014-12-09
申请号：US13460890
申请日：2012-05-01
申请人： Motoharu Miyamoto , Takahiro Ochiai
发明人： Motoharu Miyamoto , Takahiro Ochiai
CPC分类号： G11C19/28 , G09G3/3677 , G09G2300/0434 , G09G2310/0286
摘要： Provided is a gate signal line drive circuit including a shift register basic circuit for applying a high voltage for a signal high period and a low voltage for a signal low period to a gate signal line at the time of a screen display. The shift register basic circuit includes a gate line high voltage applying circuit applying a high voltage for the signal high period to the gate signal line, and a gate line low voltage applying circuit applying a low voltage to the gate signal line, wherein in the shift register basic circuit, the off-voltage is applied to the switch of the gate line low voltage applying circuit for a predetermined period at the time of a screen non-display.
摘要翻译： 提供了一种栅极信号线驱动电路，其包括用于在屏幕显示时向门信号线施加用于信号高电平的高电压和用于信号低电平的低电压的移位寄存器基本电路。 移位寄存器基本电路包括向栅极信号线施加用于信号高周期的高电压的栅极线高压施加电路和向栅极信号线施加低电压的栅极线路低压施加电路，其中， 寄存器基本电路，在屏幕不显示时，将预失真电压施加到栅极线路低压施加电路的开关一段预定时间。
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公开(公告)号：US08947338B2
公开(公告)日：2015-02-03
申请号：US13604775
申请日：2012-09-06
申请人： Motoharu Miyamoto , Takahiro Ochiai
发明人： Motoharu Miyamoto , Takahiro Ochiai
CPC分类号： G09G3/3677 , G09G2310/0281
摘要： In a driving circuit, one output circuit has a scanning signal line, a first transistor which controls electrical connection between the scanning signal line and a clock signal line which has a gate connected to a first node, the first node which is at an active potential in a first time period including a time period during which the active potential is output to the scanning signal line, a second transistor which electrically connects the first node and an inactive signal line which has a potential to open the transistor in a second time period other than the first time period, and the second transistor has a gate connected to a second node, wherein the second node has two kinds of timings to be charged for retaining the active potential.
摘要翻译： 在驱动电路中，一个输出电路具有扫描信号线，第一晶体管控制扫描信号线与连接到第一节点的栅极的时钟信号线之间的电连接，第一节点处于有效电位 在包括有效电位输出到扫描信号线的时间段的第一时间段中，将第一晶体管和第二晶体管电连接的第二晶体管，第二晶体管在第二时间段内具有电位以打开晶体管的其他 并且第二晶体管具有连接到第二节点的栅极，其中第二节点具有用于保持有效电位而被充电的两种定时。
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