公开(公告)号：US06307940B1

公开(公告)日：2001-10-23

申请号：US09104279

申请日：1998-06-25

申请人： Takahisa Yamamoto ,  Keiichi Iwamura

发明人： Takahisa Yamamoto ,  Keiichi Iwamura

IPC分类号： H04L900

CPC分类号： H04L9/0662 ,  H04L2209/125

摘要： In a cryptosystem which performs encryption/deciphering of communication text using k bits of cryptographically secure pseudo-random numbers as the block cipher key thereof, the block cipher key is updated each time j=k/m bits of new pseudo-random numbers are generated, with the j·m=k bits of pseudo-random numbers created by combining the j·(m−1) bits within the k bits of the present key and the newly generated j bits, serving as a new key, thereby shortening the updating cycle and improving the safety. Also, by sending the number of times of generation of pseudo-random numbers along with the encrypted communication text from the sending side, and by the receiving side using from the sequentially generated pseudo-random numbers, pseudo-random numbers generated after the received number of times of generation as the new key, deciphering can be performed regardless of the order to reception, in the event that a plurality of cipher texts are sequentially sent while updating the encryption key.

摘要翻译： 在使用加密安全伪随机数的k位进行通信文本的加密/解密的密码系统作为其密码密钥，每当j = k / m个比特的新伪随机数被生成时，更新块密码密钥 通过组合当前密钥的k个比特中的j（m-1）比特和新生成的j比特来创建的伪随机数的jm = k比特，从而缩短更新周期 并提高安全性。 此外，通过从发送侧发送伪随机数生成次数和加密通信文本的次数，并且通过从顺序生成的伪随机数使用接收侧，在接收到的数目之后生成的伪随机数 的生成次数作为新密钥，在多个密文被更新加密密钥的情况下，可以执行无论接收顺序如何的解密。

公开(公告)号：US5966449A

公开(公告)日：1999-10-12

申请号：US359636

申请日：1994-12-20

申请人： Keiichi Iwamura ,  Takahisa Yamamoto

发明人： Keiichi Iwamura ,  Takahisa Yamamoto

IPC分类号： G06F13/00 ,  G06F12/14 ,  G09C1/00 ,  G09C1/10 ,  H04L9/08 ,  H04L9/00

CPC分类号： H04L9/0847

摘要： In a network having a plurality of entities and a center, the center creates random numbers for all the combinations of two of the entities within the network, and delivers to each entity random numbers created for those combinations involving that entity. A sender entity selects a random number corresponding to the combination of that entity and the destination entity from a group of random numbers delivered to the sender entity, encrypts a communication text using an encryption key determined by the selected random number and sends the encrypted text to the destination entity. The destination entity selects a random number corresponding to the combination of itself and the sender entity from the random numbers delivered to the destination entity, and decodes a cipher text received using an encryption key determined by the selected random number.

摘要翻译： 在具有多个实体和中心的网络中，中心为网络内的两个实体的所有组合创建随机数，并且向每个实体递送为涉及该实体的那些组合创建的随机数。 发送者实体从发送到发送者实体的随机数组中选择与该实体和目的实体的组合相对应的随机数，使用由所选择的随机数确定的加密密钥加密通信文本，并将加密文本发送到 目的地实体。 目的实体从发送到目的地实体的随机数中选择与其本身和发送者实体的组合相对应的随机数，并使用由所选择的随机数确定的加密密钥解码接收到的密文。

公开(公告)号：US5600720A

公开(公告)日：1997-02-04

申请号：US277512

申请日：1994-07-19

申请人： Keiichi Iwamura ,  Takahisa Yamamoto

发明人： Keiichi Iwamura ,  Takahisa Yamamoto

IPC分类号： H04L9/22 ,  H04L9/26

CPC分类号： H04L9/0668 ,  H04L2209/12

摘要： In order to attain high speed and secure encryption, a communication apparatus comprises a random number generation circuit for sequentially generating random number sequences which assure difficulty in terms of amount of calculation in cryptoanalyzing the sequences based on output sequences while using a cryptographic key shared by partner stations as an initial value, and an encryption circuit for sequentially encrypting communication texts and outputting cryptograms in a transmitting station and sequentially cryptoanalyzing the cryptograms and outputting the same in a receiving station, faster than the sequential generation of the random numbers by the random number generation circuit.

摘要翻译： 为了获得高速度和安全的加密，通信装置包括随机数生成电路，用于依次产生随机数序列，这些随机数序列确保在使用由对方共享的加密密钥的情况下基于输出序列进行密码分析的序列的计算量方面的困难 电台作为初始值，以及加密电路，用于顺序地加密通信文本并在发送站中输出密码，并且在接收站中顺序地密码分析密码并将其输出，比通过随机数生成的随机数的顺序生成更快 电路。

公开(公告)号：US5828752A

公开(公告)日：1998-10-27

申请号：US402366

申请日：1995-03-13

申请人： Keiichi Iwamura ,  Takahisa Yamamoto

发明人： Keiichi Iwamura ,  Takahisa Yamamoto

IPC分类号： G09C1/00 ,  H04L9/22 ,  H04L9/00 ,  G06F7/58

CPC分类号： H04L9/0662 ,  H04L2209/12

摘要： A communication apparatus through which encryption/decryption processing can be executed at high speed includes a CPU for performing overall control of the apparatus, an encryption unit for encrypting communication data that has been stored in a RAM and outputting encrypted data, and a decryption unit for decrypting encrypted data transmitted from an external communication apparatus and storing the decrypted data in the RAM. The decryption unit issues a request to generate a series of random numbers serving as an encryption key necessary in decryption processing of the encrypted data applied thereto. A pseudo-random number generating circuit generates random numbers and delivers them to the decryption unit. The encryption unit issues a request to generate a series of random numbers serving as an encryption key necessary in encryption. The pseudo-random number generating circuit generates random numbers and delivers them to the encryption unit. The latter generates a cryptogram sentence based upon these random numbers.

摘要翻译： 可以高速执行加密/解密处理的通信装置包括用于执行装置的总体控制的CPU，用于加密存储在RAM中并输出加密数据的通信数据的加密单元，以及用于 解密从外部通信装置发送的加密数据，并将解密的数据存储在RAM中。 解密单元发出请求，生成一系列作为加密数据的加密密钥所必需的加密密钥的随机数。 伪随机数生成电路生成随机数并将其传送到解密单元。 加密单元发出请求以产生用作加密中所需的加密密钥的一系列随机数。 伪随机数生成电路生成随机数并将其传送到加密单元。 后者基于这些随机数生成密码句。

公开(公告)号：US5666419A

公开(公告)日：1997-09-09

申请号：US350110

申请日：1994-11-29

申请人： Takahisa Yamamoto ,  Keiichi Iwamura

发明人： Takahisa Yamamoto ,  Keiichi Iwamura

IPC分类号： G06F7/72 ,  H04L9/30 ,  H04L9/00

CPC分类号： G06F7/728 ,  H04L9/0662 ,  H04L9/3006 ,  H04L2209/125

摘要： In a modular multiplication circuit which operates under the conditions 0

摘要翻译： 在0

公开(公告)号：US5321752A

公开(公告)日：1994-06-14

申请号：US941236

申请日：1992-09-04

申请人： Keiichi Iwamura ,  Takahisa Yamamoto

发明人： Keiichi Iwamura ,  Takahisa Yamamoto

IPC分类号： G06F7/72 ,  G07F7/10 ,  H04K1/00

CPC分类号： G07F7/1016 ,  G06F7/722 ,  G06F7/724 ,  G06F7/728 ,  G06F7/723

摘要： A method and apparatus which enables a circuit of a small circuit scale to perform high-speed modular multiplication or modular exponentiation which are necessary in encryption or decryption in cryptic communication. To this end, modular multiplication Q=A.multidot.M mod N and modular exponentiation C=M.sup.e mod N are executed by repetition of computation of Z=U.multidot.V.multidot.R.sup.-1 mod N employing an integer R which is prime to N. The repetition of computation is executed by repeatedly operating a single circuit or by simultaneously operating a plurality of circuits of the same construction in a parallel manner.

摘要翻译： 一种方法和装置，使得小电路规模的电路能够执行在密码通信中加密或解密所必需的高速模乘或模幂运算。 为此，通过使用N为素数的整数R重复Z = UxVxR-1 mod N的计算来执行乘法Q = AxM mod N和模幂运算C = Me mod N。重复计算由 重复地操作单个电路或者以并行方式同时操作具有相同结构的多个电路。

公开(公告)号：US09014483B2

公开(公告)日：2015-04-21

申请号：US12873159

申请日：2010-08-31

申请人： Yoshinori Ito ,  Takahisa Yamamoto ,  Masami Kato

发明人： Yoshinori Ito ,  Takahisa Yamamoto ,  Masami Kato

IPC分类号： G06K9/56 ,  G06K9/62 ,  G06K9/00 ,  G06K9/46

CPC分类号： G06K9/6257 ,  G06K9/00973 ,  G06K9/4614 ,  G06K9/4642

摘要： Input information of a multidimensional array is divided into a plurality of divided areas, accumulated information is generated by calculating accumulated values at respective element positions of the input information from a corresponding reference location for each of the plurality of divided areas, and the generated accumulated information is held in a memory for each divided area. Calculation using the accumulated information is executed for a predetermined processing range. The input information is divided into the plurality of divided areas so that two neighboring divided areas have an overlapping area, and the overlapping area has a size at least in which the whole processing range fits.

摘要翻译： 多维阵列的输入信息被划分为多个分割区域，通过从多个分割区域中的每一个的相应参考位置计算输入信息的各个元素位置处的累积值来生成累积信息，并且生成累积信息 被保存在每个划分区域的存储器中。 在预定的处理范围内执行使用累积信息的计算。 输入信息被分成多个分割区域，使得两个相邻分割区域具有重叠区域，并且重叠区域具有至少整个处理范围适合的尺寸。

公开(公告)号：US08594432B2

公开(公告)日：2013-11-26

申请号：US12966725

申请日：2010-12-13

申请人： Takahisa Yamamoto ,  Masami Kato ,  Yoshinori Ito

发明人： Takahisa Yamamoto ,  Masami Kato ,  Yoshinori Ito

IPC分类号： G06K9/46 ,  G06K9/54 ,  H04N1/60

CPC分类号： G06K9/4604 ,  G06K2009/4666

摘要： An image processing apparatus includes a comparison unit that selects a pixel of interest in a processing image, and compare magnitudes of luminance value of the pixel of interest and luminance value of each of a plurality of neighboring pixels having a predetermined positional relationship with the pixel of interest; a calculation unit that calculates a feature amount of the pixel of interest based on the predetermined positional relationship between the pixel of interest and each of the plurality of neighboring pixels and a comparison result obtained by the comparison unit. For two neighboring pixels at positions which are point symmetrical with respect to the pixel of interest, the comparison unit sets that only one of the two neighboring pixels has the predetermined positional relationship.

摘要翻译： 一种图像处理装置，包括：比较单元，其选择处理图像中的感兴趣像素，并将感兴趣像素的亮度值的大小与具有预定位置关系的多个相邻像素的亮度值与 利益; 计算单元，其基于所述关注像素和所述多个相邻像素中的每一个之间的预定位置关系以及由所述比较单元获得的比较结果来计算所述感兴趣像素的特征量。 对于相对于感兴趣像素点对称的位置处的两个相邻像素，比较单元设置两个相邻像素中只有一个具有预定的位置关系。

公开(公告)号：US07937346B2

公开(公告)日：2011-05-03

申请号：US12663687

申请日：2008-06-11

申请人： Masami Kato ,  Takahisa Yamamoto ,  Yoshinori Ito

发明人： Masami Kato ,  Takahisa Yamamoto ,  Yoshinori Ito

IPC分类号： G06N3/04

CPC分类号： G06N3/08

摘要： A calculation processing apparatus for executing network calculations defined by hierarchically connecting a plurality of logical processing nodes that apply calculation processing to input data, sequentially designates a processing node which is to execute calculation processing based on sequence information that specifies an execution order of calculations of predetermined processing units to be executed by the plurality of processing nodes, so as to implement the network calculations, and executes the calculation processing of the designated processing node in the processing unit to obtain a calculation result. The calculation apparatus allocates partial areas of a memory to the plurality of processing nodes as ring buffers, and writes the calculation result in the memory while circulating a write destination of data to have a memory area corresponding to the amount of the calculation result of the processing unit as a unit.

摘要翻译： 一种用于执行网络计算的计算处理装置，所述计算处理装置执行通过将应用计算处理的多个逻辑处理节点分层连接到输入数据而定义的网络计算，依次指定执行计算处理的处理节点，该处理节点是基于指定预定的 要由多个处理节点执行的处理单元，以便实现网络计算，并且执行处理单元中的指定处理节点的计算处理以获得计算结果。 计算装置将多个处理节点的存储器的部分区域分配为环形缓冲器，并将计算结果写入存储器，同时循环数据的写入目的地以具有对应于处理的计算结果的量的存储区域 单位为单位。

公开(公告)号：US20100223219A1

公开(公告)日：2010-09-02

申请号：US12663687

申请日：2008-06-11

申请人： Masami Kato ,  Takahisa Yamamoto ,  Yoshinori Ito

发明人： Masami Kato ,  Takahisa Yamamoto ,  Yoshinori Ito

IPC分类号： G06F9/30 ,  G06N3/04 ,  G06N3/06 ,  G06F15/76 ,  G06F9/06 ,  G06F12/00

CPC分类号： G06N3/08

摘要： A calculation processing apparatus for executing network calculations defined by hierarchically connecting a plurality of logical processing nodes that apply calculation processing to input data, sequentially designates a processing node which is to execute calculation processing based on sequence information that specifies an execution order of calculations of predetermined processing units to be executed by the plurality of processing nodes, so as to implement the network calculations, and executes the calculation processing of the designated processing node in the processing unit to obtain a calculation result. The calculation apparatus allocates partial areas of a memory to the plurality of processing nodes as ring buffers, and writes the calculation result in the memory while circulating a write destination of data to have a memory area corresponding to the amount of the calculation result of the processing unit as a unit.

摘要翻译： 一种用于执行网络计算的计算处理装置，所述计算处理装置执行通过将应用计算处理的多个逻辑处理节点分层连接到输入数据而定义的网络计算，依次指定执行计算处理的处理节点，该处理节点是基于指定预定的 要由多个处理节点执行的处理单元，以便实现网络计算，并且执行处理单元中的指定处理节点的计算处理以获得计算结果。 计算装置将多个处理节点的存储器的部分区域分配为环形缓冲器，并将计算结果写入存储器，同时循环数据的写入目的地以具有对应于处理的计算结果的量的存储区域 单位为单位。