公开(公告)号：US07788565B2

公开(公告)日：2010-08-31

申请号：US12246873

申请日：2008-10-07

申请人： Takako Nishiyama ,  Hideo Ito

发明人： Takako Nishiyama ,  Hideo Ito

IPC分类号： G01R31/28

CPC分类号： G01R31/318536 ,  G01R31/318572

摘要： A semiconductor integrated circuit having a low maximum allowable operating frequency such as an analog circuit can be prevented from being destroyed during a scan test. When a scan test mode signal is “1”, output signals of a first AND circuit and a second AND circuit are fixed to a low level and an output of an OR circuit is fixed to a high level. Therefore, output signals of fourth through sixth flip-flops FF4-FF6 are not transferred to first through third analog circuits during the scan test. On the other hand, the output signals of the fourth through sixth flip-flops FF4-FF6 are transferred to the first through third analog circuits during a normal operation.

摘要翻译： 可以防止在扫描测试期间具有诸如模拟电路的低最大允许工作频率的半导体集成电路被破坏。 当扫描测试模式信号为“1”时，第一AND电路和第二AND电路的输出信号固定为低电平，OR电路的输出固定为高电平。 因此，在扫描测试期间，第四至第六触发器FF4-FF6的输出信号不被传送到第一至第三模拟电路。 另一方面，在正常操作期间，第四至第六触发器FF4-FF6的输出信号被传送到第一至第三模拟电路。