公开(公告)号：US20110249560A1

公开(公告)日：2011-10-13

申请号：US12374949

申请日：2007-07-25

申请人： Takao Nakagawa ,  Takashi Tachikawa ,  Naoyuki Nakamura ,  Tadashi Tsukamoto ,  Toshikatsu Hosoi ,  Hiroshi Kurakane

发明人： Takao Nakagawa ,  Takashi Tachikawa ,  Naoyuki Nakamura ,  Tadashi Tsukamoto ,  Toshikatsu Hosoi ,  Hiroshi Kurakane

IPC分类号： H04L12/26

CPC分类号： G06F13/1673 ,  G06F13/4059

摘要： There are provided a CPU connection circuit and a method wherein the CPU connection circuit is a circuit to be employed by two CPUs by alternately conducting a changeover between two buffers disposed therebetween to prevent an event that data processing cannot be fully executed by the CPU on the receiving side. There is included a memory controller 303 which monitors whether or not an amount of data stored by a CCPU 1 in either one of buffers 301 and 302 reaches a predetermined threshold value; when the amount of data stored by the CCPU 1 in the buffer 301, 302 reaches the threshold value, the memory controller 303 requests an ACPU 2 to acquire the data stored in the buffer and changes the storage destination of data from the CCPU to the other one of the buffers; the threshold value is a value more than a unit quantity of data which the CCPU 1 sends to the buffer 301, 302.

摘要翻译： 提供了一种CPU连接电路和一种方法，其中CPU连接电路是由两个CPU采用的电路，通过交替地在其间设置的两个缓冲器之间进行切换，以防止CPU在数据处理不能完全执行的事件 接收方。 包括存储器控制器303，其监视由缓冲器301和302中的任一个中的CCPU 1存储的数据量是否达到预定阈值; 当CCPU1存储在缓冲器301,302中的数据量达到阈值时，存储器控制器303请求ACPU 2获取存储在缓冲器中的数据，并将数据的存储目的地从CCPU改变到另一个 其中一个缓冲区; 该阈值是大于CCPU1发送到缓冲器301,302的单位数量的值。

公开(公告)号：US08397003B2

公开(公告)日：2013-03-12

申请号：US13540225

申请日：2012-07-02

申请人： Takao Nakagawa ,  Takashi Tachikawa ,  Naoyuki Nakamura ,  Tadashi Tsukamoto ,  Toshikatsu Hosoi ,  Hiroshi Kurakane

发明人： Takao Nakagawa ,  Takashi Tachikawa ,  Naoyuki Nakamura ,  Tadashi Tsukamoto ,  Toshikatsu Hosoi ,  Hiroshi Kurakane

IPC分类号： G06F13/00 ,  G06F3/00

CPC分类号： G06F13/1673 ,  G06F13/4059

摘要： There are provided a CPU connection circuit and a method by two CPUs by alternately conducting a changeover between two buffers disposed there between to prevent an event that data processing cannot be fully executed by the CPU on the receiving side. There is included a memory controller which monitors whether or not an amount of data stored by a CCPU 1 in either one of buffers 301 and 302 reaches a predetermined threshold value; when the amount of data stored by the CCPU 1 in the buffer 301, 302 reaches the threshold value, the memory controller requests an ACPU 2 to acquire the data stored in the buffer and changes the storage destination of data from the CCPU to the other one of the buffers; the threshold value is a value more than a unit quantity of data which the CCPU 1 sends to the buffer 301, 302.

摘要翻译： 通过在两个CPU之间交替地进行两个缓冲器之间的切换来提供CPU连接电路和两个CPU的方法，以防止在接收侧的CPU不能完全执行数据处理的事件。 包括存储器控制器，其监视由缓冲器301和302中的任一个中的CCPU 1存储的数据量是否达到预定阈值; 当CCPU1存储在缓冲器301,302中的数据量达到阈值时，存储器控制器请求ACPU 2获取存储在缓冲器中的数据，并将数据的存储目的地从CCPU改变到另一个 的缓冲区; 该阈值是大于CCPU1发送到缓冲器301,302的单位数量的值。

公开(公告)号：US08355326B2

公开(公告)日：2013-01-15

申请号：US12374949

申请日：2007-07-25

申请人： Takao Nakagawa ,  Takashi Tachikawa ,  Naoyuki Nakamura ,  Tadashi Tsukamoto ,  Toshikatsu Hosoi ,  Hiroshi Kurakane

发明人： Takao Nakagawa ,  Takashi Tachikawa ,  Naoyuki Nakamura ,  Tadashi Tsukamoto ,  Toshikatsu Hosoi ,  Hiroshi Kurakane

IPC分类号： H04L12/54

CPC分类号： G06F13/1673 ,  G06F13/4059

摘要： There are provided a CPU connection circuit and a method wherein the CPU connection circuit is a circuit to be employed by two CPUs by alternately conducting a changeover between two buffers disposed therebetween to prevent an event that data processing cannot be fully executed by the CPU on the receiving side. There is included a memory controller 303 which monitors whether or not an amount of data stored by a CCPU 1 in either one of buffers 301 and 302 reaches a predetermined threshold value; when the amount of data stored by the CCPU 1 in the buffer 301, 302 reaches the threshold value, the memory controller 303 requests an ACPU 2 to acquire the data stored in the buffer and changes the storage destination of data from the CCPU to the other one of the buffers; the threshold value is a value more than a unit quantity of data which the CCPU 1 sends to the buffer 301, 302.

摘要翻译： 提供了一种CPU连接电路和一种方法，其中CPU连接电路是由两个CPU采用的电路，通过交替地在其间设置的两个缓冲器之间进行切换，以防止CPU在数据处理不能完全执行的事件 接收方。 包括存储器控制器303，其监视由缓冲器301和302中的任一个中的CCPU 1存储的数据量是否达到预定阈值; 当CCPU1存储在缓冲器301,302中的数据量达到阈值时，存储器控制器303请求ACPU 2获取存储在缓冲器中的数据，并将数据的存储目的地从CCPU改变到另一个 其中一个缓冲区; 该阈值是大于CCPU1发送到缓冲器301,302的单位数量的值。

公开(公告)号：US07340624B2

公开(公告)日：2008-03-04

申请号：US10716479

申请日：2003-11-20

申请人： Hiroshi Kurakane

发明人： Hiroshi Kurakane

IPC分类号： G06F1/00

CPC分类号： G06F1/3218 ,  G06F1/08 ,  G06F1/3203 ,  G06F1/324 ,  H03L7/18 ,  Y02D10/126 ,  Y02D50/20

摘要： This invention relates to a clock control system including a CPU, a peripheral functional block for the CPU, a frequency multiplication circuit which multiplies the frequency of an input system clock and outputs the multiplied system clock, a plurality of frequency division circuits which divide the frequency of a signal output from the frequency multiplication circuit to generate clocks to be supplied to the CPU and peripheral functional block, and a clock controller which changes the frequency multiplication ratio of the frequency multiplication circuit to 1/N (positive integer) and then changes the frequency division ratio of the frequency division circuit arranged on the input stage of the peripheral functional block to 1/N in order to set the CPU to a low-power consumption mode, and a method of controlling the clock control system.

摘要翻译： 本发明涉及一种时钟控制系统，包括CPU，用于CPU的外围功能块，乘法电路，其将输入系统时钟的频率相乘并输出相乘的系统时钟;多个分频电路，其将频率 从频率倍增电路输出的信号，生成要提供给CPU和外围功能块的时钟;以及时钟控制器，其将倍频电路的倍频比改变为1 / N（正整数），然后将 为了将CPU设置为低功耗模式，配置在周边功能块的输入级上的分频电路的分频比为1 / N，以及控制时钟控制系统的方法。

公开(公告)号：US07315751B2

公开(公告)日：2008-01-01

申请号：US10393047

申请日：2003-03-21

申请人： Hiroshi Kurakane

发明人： Hiroshi Kurakane

IPC分类号： H04B1/38 ,  H04M1/00 ,  G06F3/33

CPC分类号： G06F1/1616 ,  G06F1/1686 ,  G06F2200/1637 ,  H04N1/00281 ,  H04N1/2112 ,  H04N7/147 ,  H04N2007/145

摘要： A portable apparatus includes a housing, a display device disposed on the housing, an imaging device disposed on the housing to capture an image, and a processor displaying a pointer on the display device. The processor moves the pointer in response to shift of the image caused by movement of the housing.

摘要翻译： 便携式设备包括壳体，设置在壳体上的显示装置，设置在壳体上以捕获图像的成像装置，以及在显示装置上显示指针的处理器。 处理器响应于由壳体的移动引起的图像移动而移动指针。

公开(公告)号：US07016711B2

公开(公告)日：2006-03-21

申请号：US10284324

申请日：2002-10-31

申请人： Hiroshi Kurakane

发明人： Hiroshi Kurakane

IPC分类号： H04B1/38

CPC分类号： H04M1/7258 ,  G06F3/0426 ,  H04M1/0214 ,  H04M1/0272 ,  H04M2250/22

摘要： A cellular phone of folded type has a cover panel and a base panel coupled by a hinge for swiveling of the cover panel between a folded state and a developed state. The base panel mounts thereon a touch-sensitive panel whereas the cover panel mounts an image projector for projecting an image of keyboard information onto the touch-sensitive panel. The keyboard information includes a label for each of the keypads for designating the function of the keypad, and switched based on the input mode of the cellular phone.