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公开(公告)号：US20110284996A1
公开(公告)日：2011-11-24
申请号：US13109086
申请日：2011-05-17
IPC分类号： H01L23/58 , H01L21/4763
CPC分类号： H01L23/5222 , H01L21/7682 , H01L21/76838 , H01L23/528 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a semiconductor device includes a substrate, and a plurality of interconnects provided in the same interconnect layer above the substrate. The device further includes a plurality of insulators provided so as to be buried between the plurality of interconnects. Moreover, the plurality of interconnects include an interconnect group in which 2N or more interconnects are successively arrayed so that correlation coefficients of line edge roughness (LER) between both side surfaces of the respective interconnects are positive, where N is an integer of 4 or more.
摘要翻译： 在一个实施例中，半导体器件包括衬底和设置在衬底上方的相同互连层中的多个互连。 该装置还包括多个绝缘体，其设置成埋在多个互连件之间。 此外，多个互连包括互连组，其中连续排列2N个或更多个互连，使得各互连的两个侧表面之间的线边缘粗糙度（LER）的相关系数为正，其中N为4或更大的整数 。
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公开(公告)号：US08610282B2
公开(公告)日：2013-12-17
申请号：US13109086
申请日：2011-05-17
IPC分类号： H01L23/13
CPC分类号： H01L23/5222 , H01L21/7682 , H01L21/76838 , H01L23/528 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a semiconductor device includes a substrate, and a plurality of interconnects provided in the same interconnect layer above the substrate. The device further includes a plurality of insulators provided so as to be buried between the plurality of interconnects. Moreover, the plurality of interconnects include an interconnect group in which 2N or more interconnects are successively arrayed so that correlation coefficients of line edge roughness (LER) between both side surfaces of the respective interconnects are positive, where N is an integer of 4 or more.
摘要翻译： 在一个实施例中，半导体器件包括衬底和设置在衬底上方的相同互连层中的多个互连。 该装置还包括多个绝缘体，其设置成埋在多个互连件之间。 此外，多个互连包括互连组，其中连续排列2N个或更多个互连，使得各互连的两个侧表面之间的线边缘粗糙度（LER）的相关系数为正，其中N为4或更大的整数 。
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