公开(公告)号：US20050157872A1

公开(公告)日：2005-07-21

申请号：US10984665

申请日：2004-11-09

申请人： Takatoshi Ono ,  Natsume Matsuzaki ,  Yuichi Futa

发明人： Takatoshi Ono ,  Natsume Matsuzaki ,  Yuichi Futa

IPC分类号： H04L9/30 ,  H04L9/32 ,  H04L9/00

CPC分类号： H04L9/3249 ,  H04L9/302 ,  H04L2209/56

摘要： An RSA decryption apparatus that is used in an IC card or the like counters a differential fault attack. The RSA decryption apparatus computes at high speed a public key used in data verification, without having to obtain the public key from an external source. The RSA decryption apparatus includes a remainder computation unit 412 that calculates dp=d mod (p−1), and an inverse computation unit 414 that finds an inverse of dp over a residue field with p−1 as a modulus. The RSA decryption apparatus verifies a decipher text with use of the inverse of dp as the public key. The reduced bit count in inverse computation compared to if the inverse of d is found as the public key increases computing speed.

摘要翻译： 在IC卡等中使用的RSA解密装置反映差分故障攻击。 RSA解密装置高速计算用于数据验证的公开密钥，而不必从外部源获得公共密钥。 RSA解密装置包括：计算d≠p mod（p-1）的余数计算单元412，以及求出d∧ 在p-1作为模量的残留场上。 RSA解密装置使用公开密钥d D的倒数验证解密文本。 与如果将d的倒数作为公开密钥发现的逆计算相比，减少的比特数增加了计算速度。

公开(公告)号：US07167559B2

公开(公告)日：2007-01-23

申请号：US10105480

申请日：2002-03-25

申请人： Takatoshi Ono ,  Natsume Matsuzaki ,  Toshihisa Nakano

发明人： Takatoshi Ono ,  Natsume Matsuzaki ,  Toshihisa Nakano

IPC分类号： H04K1/00

CPC分类号： G06F7/723 ,  G06F7/725 ,  G06F2207/7285

摘要： In an exponentiation device, a relatively large table is generated outside of a coprocessor so as to enable high-speed exponentiation to be performed using the small window method. The selection of data from the table and transfer of data to the coprocessor are conducted in parallel with a multiple-length arithmetic operation performed in the coprocessor. So as to avoid bottlenecks occurring in the data transfer between a CPU and the coprocessor, two data banks are provided in the coprocessor for storing the data to be used in the arithmetic operation. By providing two banks in the coprocessor, it is possible to use one for transferring data while data stored in the other is being used in the arithmetic operation. When the operation using the stored data has been completed, the banks are switched, and the arithmetic operation is then repeated using the newly transferred data while at the same time conducting data transfer in readiness for the following operation.

摘要翻译： 在求幂装置中，在协处理器之外产生相对大的表，以便能够使用小窗口方法执行高速乘法运算。 从协议处理器中执行的多长度算术运算并行地进行从表中选择数据并将数据传送到协处理器。 为了避免在CPU和协处理器之间的数据传输中出现瓶颈，在协处理器中提供两个数据组，用于存储要在算术运算中使用的数据。 通过在协处理器中提供两个存储体，可以使用一个用于传送数据，而另一个存储的数据正在算术运算中使用。 当使用存储的数据的操作已经完成时，这些存储体被切换，然后使用新传送的数据重复算术运算，同时进行数据传送以备以下操作。

公开(公告)号：US06963644B1

公开(公告)日：2005-11-08

申请号：US09544069

申请日：2000-04-06

申请人： Natsume Matsuzaki ,  Yasuo Okumura ,  Takatoshi Ono

发明人： Natsume Matsuzaki ,  Yasuo Okumura ,  Takatoshi Ono

IPC分类号： G06F7/00 ,  G06F7/38 ,  G06F7/57 ,  G06F7/72

CPC分类号： G06F7/57 ,  G06F7/72 ,  G06F7/728

摘要： A multi-word arithmetic device, capable of executing a variety of types of multi-word arithmetic required for elliptic curve cryptology, includes the following. A memory 40, formed from two dual-port memories 41 and 42, temporarily stores n-word integers on which calculation is performed, and a calculation result. An arithmetic unit 20 executes two or more types of calculation, including addition and multiplication, on each word, and outputs a one-word result. A memory input/output unit 30 supplies a maximum of three pieces of one-word data from the memory 40 to the arithmetic unit 20, while simultaneously storing a one-word calculation result from the arithmetic unit 20 in the memory 40. A control unit 10 controls the arithmetic unit 20 and the memory input/output unit 30 so as to have the arithmetic unit execute one of modular addition and Montgomery reduction on n words.

摘要翻译： 能够执行椭圆曲线密码学所需的各种多字运算的多字算术装置包括以下。 由两个双端口存储器41和42形成的存储器40临时存储执行计算的n字整数和计算结果。 算术单元20对每个单词执行包括加法和乘法的两种或多种类型的计算，并输出单字结果。 存储器输入/输出单元30将来自存储器40的最多三个一字数据提供给运算单元20，同时将来自运算单元20的单字计算结果存储在存储器40中。 控制单元10控制运算单元20和存储器输入/输出单元30，以使算术单元执行n个单词的模块加法和蒙哥马利减少之一。

公开(公告)号：US07388957B2

公开(公告)日：2008-06-17

申请号：US10763958

申请日：2004-01-23

申请人： Takatoshi Ono ,  Natsume Matsuzaki

发明人： Takatoshi Ono ,  Natsume Matsuzaki

IPC分类号： H04K1/00

CPC分类号： G06F7/725 ,  G06F2207/7271

摘要： Provided is an elliptic curve exponentiation apparatus that can counter the DFA when an elliptic curve exponentiation technique is used. A computation result verification unit 127 receives, as a computation result, an exponentiation-result-point (X, Y) from an elliptic curve computation unit 124. The computation result verification unit 127 computes X3+a×X+b, and computes Y2, and outputs the received exponentiation-result-point when judging that Y2=X3+a×X+b, and does not output the received exponentiation-result-point when not judging that Y2=X3+a×X+b.

摘要翻译： 提供了当使用椭圆曲线求幂技术时可以对抗DFA的椭圆曲线求幂装置。 计算结果验证单元127从椭圆曲线计算单元124接收作为计算结果的求幂结果点（X，Y）。计算结果验证单元127计算X 3+ axx + b，并计算Y 2，并且当判定Y 2 = X 3 + axX + b时输出接收的求幂结果点 ，并且在不判断Y 2 = X 3 3 + ax X + b时不输出接收的求幂结果点。

公开(公告)号：US06567832B1

公开(公告)日：2003-05-20

申请号：US09523486

申请日：2000-03-10

申请人： Takatoshi Ono ,  Natsume Matsuzaki

发明人： Takatoshi Ono ,  Natsume Matsuzaki

IPC分类号： G06F738

CPC分类号： G06F7/723 ,  G06F7/725 ,  G06F2207/7285

摘要： An exponent preprocessing unit preprocesses an n-bit exponent k and exponentiates a base A by the preprocessed exponent k. A bit string storing unit stores a bit string including a sign bit and the exponent k. A reading unit reads a bit pattern composed of the sign bit and a bit sequence made up of a predetermined number of bits. A bit pattern generating unit generates a new bit pattern from the read bit pattern. An operation pattern specifying unit specifies an operation pattern based on the read bit pattern. An operating unit performs an operation according to the specified operation pattern and writes the new bit pattern over the previous bit pattern. The reading unit reads a next bit sequence starting from a different bit in the bit string storing unit. A repeat controlling unit repeats these procedures n+1 times.

摘要翻译： 指数预处理单元预处理n位指数k，并且通过预处理指数k对基A进行指数。 位串存储单元存储包括符号位和指数k的位串。 读取单元读取由符号位组成的位模式和由预定位数组成的位序列。 位模式生成单元从读位模式生成新的位模式。 操作模式指定单元基于读取位模式指定操作模式。 操作单元根据指定的操作模式执行操作，并将新位模式写入先前的位模式。 读取单元从比特串存储单元中的不同位开始读取下一个比特序列。 重复控制单元重复这些步骤n + 1次。

公开(公告)号：US06366940B1

公开(公告)日：2002-04-02

申请号：US09261614

申请日：1999-03-02

申请人： Takatoshi Ono ,  Natsume Matsuzaki ,  Hiroshi Kashiwa

发明人： Takatoshi Ono ,  Natsume Matsuzaki ,  Hiroshi Kashiwa

IPC分类号： G06F738

CPC分类号： G06F7/722

摘要： The modular multiplication apparatus includes a residue calculating unit, a multiplier division unit, a partial product calculation unit, an accumulation unit, a correction unit, and a control unit. The residue calculating unit recurrently calculates intermediate values in sequence. The residue calculating unit obtains the multiplicand as the intermediate value first time, and at the second time and after, calculates residues or congruent values of the modulo P multiplication of the intermediate values being preceding intermediate values left-shifted s bits. The multiplier division unit divides the multiplier into a plurality of s-bit partial multipliers in order from lower bits. The partial product calculation unit calculates partial products of intermediate values and partial multipliers in sequence. The accumulation unit and the correction unit accumulate the partial products while correcting them under the control of the control unit. The residue calculating unit includes a table unit. The table unit prestores residues of modulo p multiplications of (m-bit value) *2k, where the m-bit values respectively correspond to values from decimal values 0 to 2m−1. The residue calculating unit refers to the table unit to read out a residue corresponding to higher m bits adjacent to the lower k bits of the left-shifted intermediate value. The residue calculating unit calculates a residue or a congruent value of modulo p multiplications of the left-shifted intermediate value by adding up the read-out residue and the lower k bits.

摘要翻译： 模乘装置包括残差计算单元，乘法器分割单元，部分乘积计算单元，累积单元，校正单元和控制单元。 残差计算单元依次反复计算中间值。 残差计算单元获得作为第一时间的中间值的被乘数，并且在第二时间和之后，计算作为前一中间值左移s位的中间值的模P乘法的残差或全等值。 乘法器分割单元按照从低位开始的顺序将乘法器分成多个s位部分乘法器。 部分乘积计算单元依次计算中间值和部分乘法器的部分乘积。 累积单元和校正单元在控制单元的控制下对其进行校正，累积部分乘积。 残差计算单元包括台单元。 表单元预先存储（m位值）* 2k的模p乘法残差，其中m位值分别对应于从小数值0到2m-1的值。 残差计算单元参考表单元读出与左移中间值的低k位相邻的较高m位对应的残差。 残差计算单元通过将读出残差和低k位相加来计算左移中间值的模p乘法的残差或全等值。

公开(公告)号：US07130422B2

公开(公告)日：2006-10-31

申请号：US10120489

申请日：2002-04-12

申请人： Yuichi Futa ,  Takatoshi Ono ,  Motoji Ohmori

发明人： Yuichi Futa ,  Takatoshi Ono ,  Motoji Ohmori

IPC分类号： H04L9/30 ,  G06F4/58 ,  G06F7/38

CPC分类号： G06F7/72 ,  G06F2207/7204 ,  H04L9/3033 ,  H04L2209/08 ,  H04L2209/80

摘要： An information security device receives an input of prime q, and generates prime N that is larger than prime q. In the information security device, a partial information setting unit generates number u such that 2×u×q+1≠0 mod Li (i=1, 2, . . . , n). A random number generating unit generates random number R′. A judgement target generating unit generates R=u+L1×L2× . . . ×Ln×R′ and N=2×R×q+1, using number u and random number R′. A primality judging unit judges the primality of number N, using numbers N and R generated by the judgement target generating unit.

摘要翻译： 信息安全设备接收素数q的输入，并产生大于素数q的素数N. 在信息安全装置中，部分信息设定单元生成数字u，使得2xuxq + 1 <> 0 mod L i（i = 1,2，...，n）。 随机数生成单元生成随机数R'。 判断目标产生单元生成R = u + L 1 xL 2 x x。 。 。 xL xR'和N = 2xRxq + 1，使用数u和随机数R'。 原语判断单元使用由判断目标生成单元生成的数字N和R来判断数字N的原语。

公开(公告)号：US09158287B2

公开(公告)日：2015-10-13

申请号：US14148902

申请日：2014-01-07

申请人： Takatoshi Ono

发明人： Takatoshi Ono

IPC分类号： G04G7/00 ,  G04R20/18 ,  G04R20/14 ,  G04R20/00 ,  G04R20/30

CPC分类号： G04R20/18 ,  G04G7/00 ,  G04R20/00 ,  G04R20/14 ,  G04R20/30

摘要： An information processing apparatus includes: a communication device communicating with an external device and a clock server; a first clock measuring a local time; a second clock measuring a time based on time information from the clock server; a storage device storing setting information; and a controller performing: when receiving the time information from the external device, judging whether a specified condition is met; when the specified condition is met, setting a time indicated by the time information to the first clock as the local time; when the specified condition is met, controlling the first clock to measure the local time, without the controller setting the time to the first clock as the local time; setting the time indicated by the time information to the second clock and setting a time determined based on the time of the second clock and the setting information to the first clock.

摘要翻译： 一种信息处理设备，包括：与外部设备和时钟服务器通信的通信设备; 测量当地时间的第一时钟; 基于来自时钟服务器的时间信息测量时间的第二时钟; 存储设备信息的存储设备; 以及控制器，执行：当从所述外部设备接收到所述时间信息时，判断是否满足规定的条件; 当满足指定条件时，将由时间信息指示的时间设置为第一时钟作为本地时间; 当满足指定条件时，控制第一个时钟来测量本地时间，而控制器将时间设置为第一个时钟作为本地时间; 将由时间信息指示的时间设置为第二时钟，并将基于第二时钟的时间确定的时间和设置信息设置为第一时钟。

公开(公告)号：US08817284B2

公开(公告)日：2014-08-26

申请号：US13617190

申请日：2012-09-14

申请人： Takatoshi Ono

发明人： Takatoshi Ono

IPC分类号： G06F3/12

CPC分类号： H04N1/00474 ,  G03G15/502 ,  H04N1/00408 ,  H04N1/00411 ,  H04N1/00424 ,  H04N1/00435 ,  H04N1/00477 ,  H04N1/00482 ,  H04N2201/0039 ,  H04N2201/0094

摘要： An image forming apparatus, including: a display device; a coordinate detecting portion which detects a directed coordinate in a display area including a first area in which is displayed a hierarchy image including uppermost-level images and lower-level images; a first display control section; a second display control section to display at least one first button image; and a third display control section, the uppermost-level images including: a first image in which is displayed at least one second button image; a second image in which is displayed at least one third button image; and a third image, wherein, where the directed coordinate is one of coordinates corresponding to the first through third button images, the third control section displays a lower-level image corresponding to a button image corresponding to the directed coordinate, and wherein the first control section executes processing to display the one uppermost-level image so as to be changed.

摘要翻译： 一种图像形成装置，包括：显示装置; 检测包括显示包括最上层图像和下位图像的层次图像的第一区域的显示区域中的定向坐标的坐标检测部分; 第一显示控制部; 第二显示控制部分，用于显示至少一个第一按钮图像; 和第三显示控制部分，所述最上层图像包括：显示至少一个第二按钮图像的第一图像; 其中显示至少一个第三按钮图像的第二图像; 和第三图像，其中，在所述指向坐标是与所述第一至第三按钮图像相对应的坐标之一中的情况下，所述第三控制部显示与对应于所述定向坐标的按钮图像相对应的下一级图像，并且其中，所述第一控制 部分执行处理以显示一个最上层图像以便改变。

公开(公告)号：US08736884B2

公开(公告)日：2014-05-27

申请号：US13617302

申请日：2012-09-14

申请人： Takatoshi Ono

发明人： Takatoshi Ono

IPC分类号： G06F3/12

CPC分类号： H04N1/00474 ,  H04N1/00482 ,  H04N1/00503 ,  H04N2201/0094

摘要： An image processor includes a display. The display displays a preset-setting-group selection screen containing a plurality of icons respectively corresponding to preset-setting groups such that one icon is displayed in a manner indicative of a selected state while at least one icon other than the one icon is displayed in a manner that is indicative of an unselected state. When any of set values of a preset-setting group corresponding to the one icon having been displayed in the manner indicative of the selected state, the display displays a preset-setting-group-updated screen containing the one icon displayed in the manner indicative of the selected state on the preset-setting-group selection screen and not containing the at least one icon in the manner indicative of the unselected state on the preset-setting-group selection screen.

摘要翻译： 图像处理器包括显示器。 显示器显示包含分别对应于预置设置组的多个图标的预设设置组选择屏幕，使得以指示所选状态的方式显示一个图标，而除了一个图标之外的至少一个图标被显示 指示未选择状态的方式。 当以指示所选状态的方式显示对应于一个图标的预设设置组的设置值中的任何一个时，显示器显示包含以指示的方式显示的方式显示的一个图标的预设设置组更新屏幕 预选设定组选择画面上的选择状态，并且以表示预置设定组选择画面上的未选择状态的方式不包含至少一个图标。