公开(公告)号：US5546135A

公开(公告)日：1996-08-13

申请号：US22303

申请日：1993-02-25

申请人： Takuji Okamoto ,  Masanori Hamada ,  Kenta Sokawa ,  Kazuya Uyeda ,  Hideaki Yamauchi

发明人： Takuji Okamoto ,  Masanori Hamada ,  Kenta Sokawa ,  Kazuya Uyeda ,  Hideaki Yamauchi

IPC分类号： H04N5/14 ,  H04N5/57

CPC分类号： H04N5/142

摘要： A contour restoration circuit comprises an input terminal, a plural of delay circuits connected to the input terminal in series, a maximum value detection circuit, a minimum value detection circuit, a mean value calculating the mean value from the maximum and minimum values, a subtractor for subtracting the mean value from the input video signal, a gain controller for the subtracted signal, an adder for adding the gain controlled signal to the input video signal and an output terminal.

摘要翻译： 轮廓恢复电路包括输入端子，串联连接到输入端子的多个延迟电路，最大值检测电路，最小值检测电路，从最大值和最小值计算平均值的平均值，减法器 用于从输入视频信号中减去平均值，减法信号的增益控制器，用于将增益受控信号与输入视频信号相加的加法器和输出端。

公开(公告)号：US5668606A

公开(公告)日：1997-09-16

申请号：US616283

申请日：1996-03-15

申请人： Takuji Okamoto ,  Masanori Hamada ,  Kenta Sokawa ,  Kazuya Uyeda ,  Hideaki Yamauchi

发明人： Takuji Okamoto ,  Masanori Hamada ,  Kenta Sokawa ,  Kazuya Uyeda ,  Hideaki Yamauchi

IPC分类号： H04N5/14 ,  H04N5/208

CPC分类号： H04N5/142

摘要： A contour restoration apparatus has a plurality of delay circuits connected in series. Maximum and minimum value detection circuits detect maximum and minimum values among an input video signal and output signals of the delay circuits. A mean value circuit is used to calculate a mean value of the of the maximum and minimum values. The mean value is subtracted from a delayed signal having a delay time of one-half of a delay time obtained from all the delay circuits. An adder is used to add the result of the subtraction to the delayed signal. A non-linear processing circuit processes the output of said adder and the maximum and minimum values. The non-linear circuit outputs the output signal of the adder, if the output signal of said adder is between the maximum value and the minimum value. A contour extraction circuit multiplies a signal located centrally among the input video signal, the output signals and the signals located before and after the input signal with a predetermined coefficient. An adder adds the multiplied signals. Another adder adds the result of multiplied signal and the centrally located signal. A contour amplitude circuit detects a difference between the maximum and minimum values and outputs a coefficient determined according to the difference detected. A mixer mixes the output of the non-linear processing circuit and the output of the another adder.

摘要翻译： 轮廓恢复装置具有串联连接的多个延迟电路。 最大值和最小值检测电路检测输入视频信号和延迟电路的输出信号之间的最大值和最小值。 平均值电路用于计算最大值和最小值的平均值。 从具有从所有延迟电路获得的延迟时间的二分之一的延迟时间的延迟信号中减去平均值。 加法器用于将减法的结果加到延迟信号上。 非线性处理电路处理所述加法器的输出和最大值和最小值。 如果所述加法器的输出信号在最大值和最小值之间，则非线性电路输出加法器的输出信号。 轮廓提取电路将位于输入视频信号之间的中心的信号，输出信号和位于输入信号之前和之后的信号以预定系数相乘。 加法器加上相乘的信号。 另一个加法器将乘法信号的结果和位于中心的信号相加。 轮廓振幅电路检测最大值和最小值之间的差异，并输出根据检测到的差异确定的系数。 混频器混合非线性处理电路的输出和另一加法器的输出。

公开(公告)号：US5353069A

公开(公告)日：1994-10-04

申请号：US59266

申请日：1993-05-11

申请人： Kazuo Kobo ,  Kazuya Uyeda ,  Robert Ho ,  Takashi Yamaguchi

发明人： Kazuo Kobo ,  Kazuya Uyeda ,  Robert Ho ,  Takashi Yamaguchi

IPC分类号： H04N5/21 ,  H04N5/213

CPC分类号： H04N5/211

摘要： A waveform equalizing system includes a clock reproducing phase locked loop circuit for reproducing a clock signal from a television signal; a transversal filter; a first selector circuit for alternatively passing the television signal or an output of a first memory to the transversal filter; a CPU for extracting reference signals contained in the television signal from the input and output of the transversal filter through two second memories respectively and for performing a synchronous addition of the same; the first memory for storing a reference signal processed by the synchronous addition; and a second selector circuit for alternatively delivering the television signal or an output of the transversal filter in response to a control signal from the CPU. The CPU is arranged for calculating a phase difference between the clock signal of the clock reproducing circuit and its ideal form from the reference signal processed by the synchronous addition and controlling a clock signal phase of the clock reproducing phase locked loop circuit to correct the phase difference.

摘要翻译： 波形均衡系统包括用于从电视信号再现时钟信号的时钟再生锁相环电路; 横向过滤器 第一选择器电路，用于交替地将电视信号或第一存储器的输出传递到横向滤波器; CPU，用于通过两个第二存储器分别从横向滤波器的输入和输出中提取包含在电视信号中的参考信号，并且用于执行其同步相加; 用于存储通过同步加法处理的参考信号的第一存储器; 以及第二选择器电路，用于响应于来自CPU的控制信号交替地传送电视信号或横向滤波器的输出。 CPU被配置为从由同步加法处理的参考信号和时钟再现锁相环电路的时钟信号相位计算时钟再现电路的时钟信号与其理想形式之间的相位差，以校正相位差 。