公开(公告)号：US07230856B1

公开(公告)日：2007-06-12

申请号：US11259342

申请日：2005-10-24

申请人： Rajesh Venugopal ,  Greg J. Landry ,  Tao Peng

发明人： Rajesh Venugopal ,  Greg J. Landry ,  Tao Peng

IPC分类号： G11C7/00

CPC分类号： G11C7/1051 ,  G11C7/1012 ,  G11C7/106

摘要： Embodiments of a high-speed multiplexer latch are described. The multiplexer latch may include a multiplexer and a latch coupled to each other at a first node and a second node. The multiplexer latch may further include an inverter having an input and an output. The input of the inverter is also coupled to the latch at the second node and the output of the inverter is coupled to a data output terminal. The multiplexer latch may further include a bypass circuit coupled to the latch at the first node and the data output terminal.

摘要翻译： 描述高速多路复用器锁存器的实施例。 复用器锁存器可以包括多路复用器和在第一节点和第二节点处彼此耦合的锁存器。 复用器锁存器还可以包括具有输入和输出的反相器。 反相器的输入端还耦合到第二节点处的锁存器，并且反相器的输出耦合到数据输出端子。 复用器锁存器还可以包括耦合到第一节点处的锁存器和数据输出端子的旁路电路。

公开(公告)号：US07408827B1

公开(公告)日：2008-08-05

申请号：US11303067

申请日：2005-12-14

申请人： Tao Peng ,  Rajesh Venugopal

发明人： Tao Peng ,  Rajesh Venugopal

IPC分类号： G11C7/02

CPC分类号： G11C7/08 ,  G11C7/062

摘要： Disclosed herein is a current sense amplifier (ISA) circuit with increased speed, less insensitivities to process variation, better stability and improved output signal swing. According to one embodiment, the ISA circuit described herein may include a pair of output nodes and a first pair of load transistors, each coupled between a different one of the output nodes and ground for pulling the output nodes down to a first voltage value at the beginning of a sense cycle. In addition, a pulse generation circuit is included for activating the first pair of load transistors at the beginning of the sense cycle and deactivating the first pair of load transistors once the first voltage is reached. When activated, the first pair of load transistors provide a relatively low resistance current path between the output nodes and ground. This decreases the output node discharge time and increases the overall speed of the sense amp without compromising circuit stability and output swing.

摘要翻译： 本文公开了具有增加的速度的电流读出放大器（ISA）电路，对处理变化的不敏感性，更好的稳定性和改善的输出信号摆幅。 根据一个实施例，本文描述的ISA电路可以包括一对输出节点和第一对负载晶体管，每对负载晶体管耦合在不同的输出节点和地之间，用于将输出节点向下拉到第一电压值 感觉周期的开始 此外，包括在感测周期开始时激活第一对负载晶体管的脉冲发生电路，一旦达到第一电压就停用第一对负载晶体管。 当被激活时，第一对负载晶体管在输出节点和地之间提供相对较低的电阻电流路径。 这会降低输出节点放电时间，并增加感测放大器的总体速度，而不会影响电路稳定性和输出摆幅。

公开(公告)号：US07365569B1

公开(公告)日：2008-04-29

申请号：US11408687

申请日：2006-04-20

申请人： Rajesh Venugopal

发明人： Rajesh Venugopal

IPC分类号： H03K19/0175

CPC分类号： H03K3/35613

摘要： Embodiments of a high-speed level shifter are described. The level shifter may include a first transistor having a drain, a source, and a gate and a second transistor having a drain, a source, and a gate. The first and second transistors may be operable to receive a pair of differential signals. The level shifter may further include a third transistor having a drain, a source, and a gate, the drain of the third transistor directly coupled to the source of the first transistor, and the source of the third transistor directly coupled to the source of the second transistor. The gate of the third transistor is driven by a level-shifted version of an output voltage generated from the pair of differential signals.

摘要翻译： 对高速电平移位器的实施例进行说明。 电平移位器可以包括具有漏极，源极和栅极的第一晶体管和具有漏极，源极和栅极的第二晶体管。 第一和第二晶体管可以用于接收一对差分信号。 电平移位器还可以包括具有漏极，源极和栅极的第三晶体管，第三晶体管的漏极直接耦合到第一晶体管的源极，并且第三晶体管的源极直接耦合到源极 第二晶体管。 第三晶体管的栅极由从该对差分信号产生的输出电压的电平移位版本驱动。