公开(公告)号：US07230856B1

公开(公告)日：2007-06-12

申请号：US11259342

申请日：2005-10-24

申请人： Rajesh Venugopal ,  Greg J. Landry ,  Tao Peng

发明人： Rajesh Venugopal ,  Greg J. Landry ,  Tao Peng

IPC分类号： G11C7/00

CPC分类号： G11C7/1051 ,  G11C7/1012 ,  G11C7/106

摘要： Embodiments of a high-speed multiplexer latch are described. The multiplexer latch may include a multiplexer and a latch coupled to each other at a first node and a second node. The multiplexer latch may further include an inverter having an input and an output. The input of the inverter is also coupled to the latch at the second node and the output of the inverter is coupled to a data output terminal. The multiplexer latch may further include a bypass circuit coupled to the latch at the first node and the data output terminal.

摘要翻译： 描述高速多路复用器锁存器的实施例。 复用器锁存器可以包括多路复用器和在第一节点和第二节点处彼此耦合的锁存器。 复用器锁存器还可以包括具有输入和输出的反相器。 反相器的输入端还耦合到第二节点处的锁存器，并且反相器的输出耦合到数据输出端子。 复用器锁存器还可以包括耦合到第一节点处的锁存器和数据输出端子的旁路电路。

公开(公告)号：US07616513B1

公开(公告)日：2009-11-10

申请号：US11262412

申请日：2005-10-28

申请人： Tao Peng ,  Greg J. Landry

发明人： Tao Peng ,  Greg J. Landry

IPC分类号： G11C7/02

CPC分类号： G11C7/062 ,  G11C7/08 ,  G11C2207/063

摘要： A memory device, current sense amplifier and method of operating the same are disclosed herein. In accordance with one embodiment, the current sense amplifier circuit may include a pair of cross-coupled transistors, a pair of output nodes and a first pair of load transistors. The pair of cross-coupled transistors may be coupled for receiving a pair of differential currents and for generating a pair of differential voltages, which may then be supplied to the pair of output nodes. The first pair of load transistors may have mutually-connected gate terminals, mutually-connected drain terminals, and a source terminal coupled to a different one of the output nodes. In a unique aspect of the invention, an equalization transistor may coupled between the pair of output nodes for equalizing the pair of differential voltages for a predetermined amount of time at the beginning of a sense cycle. As such, the equalization transistor may be added to prevent the current sense amplifier circuit from generating erroneous results during the predetermined time period.

摘要翻译： 本文公开了一种存储器件，电流检测放大器及其操作方法。 根据一个实施例，电流检测放大器电路可以包括一对交叉耦合晶体管，一对输出节点和第一对负载晶体管。 该对交叉耦合晶体管可以被耦合用于接收一对差分电流并且用于产生一对差分电压，然后可以将这些差分电压提供给该对输出节点。 第一对负载晶体管可以具有相互连接的栅极端子，相互连接的漏极端子以及耦合到不同的输出节点的源极端子。 在本发明的独特方面中，均衡晶体管可以耦合在该对输出节点之间，以便在感测周期开始时将一对差分电压平均预定的时间量。 因此，可以添加均衡晶体管以防止电流读出放大器电路在预定时间段期间产生错误的结果。

公开(公告)号：US06563437B1

公开(公告)日：2003-05-13

申请号：US09677255

申请日：2000-10-02

申请人： Greg J. Landry ,  Timothy M. Lacey

发明人： Greg J. Landry ,  Timothy M. Lacey

IPC分类号： H03M734

CPC分类号： G06F17/5054

摘要： According to one embodiment, a method for programming a programmable logic device (PLD) may include reading configuration data from a memory device to program a first portion of a PLD to function as a data decompression circuit (304, 308). Compressed configuration data may then be read and decompressed by the first portion and used to program a second portion (310, 312, 315) with a user determined function. A first portion may then be reprogrammed with a user determined function (320, 324).

摘要翻译： 根据一个实施例，一种用于编程可编程逻辑器件（PLD）的方法可以包括从存储器件读取配置数据以编程PLD的第一部分以用作数据解压缩电路（304,308）。 然后可以由第一部分读取和解压缩压缩的配置数据，并且用于以用户确定的功能对第二部分（310,312,315）进行编程。 然后可以用用户确定的功能重新编程第一部分（320,324）。

公开(公告)号：US06507932B1

公开(公告)日：2003-01-14

申请号：US09347074

申请日：1999-07-02

申请人： Greg J. Landry ,  Alan Hawse

发明人： Greg J. Landry ,  Alan Hawse

IPC分类号： G06F1750

CPC分类号： G06F17/5036

摘要： A method of converting or translating a layout or schematic netlist to a simulation netlist, comprising the steps of identifying net-shorting elements in the layout or schematic netlist and automatically replacing at least one such net-shorting element with an RC network to generate the simulation netlist.

摘要翻译： 一种将布局或示意图网表转换或转换为模拟网表的方法，包括以下步骤：识别布局或示意图网表中的网络短路元件，并用RC网络自动替换至少一个这样的网络短路元件以产生模拟 网表。

公开(公告)号：US5835970A

公开(公告)日：1998-11-10

申请号：US576505

申请日：1995-12-21

申请人： Greg J. Landry ,  Shailesh Shah

发明人： Greg J. Landry ,  Shailesh Shah

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： An improved burst address generator that is coupled to a memory array receives as its inputs a N-bit start address and dynamically generates a burst sequence of 2.sup.N decoded addresses. The burst address generator is responsive to a mode-select signal that determines whether the burst address generator operates in a linear mode or a non-linear mode. A decoder is provided for decoding the start address. A wrap-around up-down 2.sup.N -bit shift register, coupled to the address decoder, receives the decoded start address from the address decoder and dynamically provides the proper burst address sequences in accordance to the selected mode. A start address storage element is also coupled to the shift register and the address decoder to keep track of the start address.

摘要翻译： 耦合到存储器阵列的改进的突发地址发生器接收N位起始地址作为其输入，并动态地产生2N个解码地址的突发序列。 脉冲串地址发生器响应于模式选择信号，该模式选择信号确定突发地址发生器是以线性模式还是非线性模式操作。 提供了解码器来解码起始地址。 耦合到地址解码器的环绕上下2N位移位寄存器从地址解码器接收解码的起始地址，并根据所选择的模式动态地提供适当的突发地址序列。 起始地址存储元件还耦合到移位寄存器和地址解码器以跟踪起始地址。

公开(公告)号：US06411140B1

公开(公告)日：2002-06-25

申请号：US09307063

申请日：1999-05-07

申请人： Greg J. Landry

发明人： Greg J. Landry

IPC分类号： H03L700

CPC分类号： G06F13/28 ,  G11C7/22 ,  G11C8/06 ,  H03K19/0013 ,  H03K19/00323

摘要： The integrated circuit includes an input path circuit with an address path having an input buffer for providing address signals to a register. A separate clock path having an input buffer provides a clock signal for clocking the register. The input buffers of both the address path and the clock path include input buffer cells configured to reduce timing delay differences caused by process variations while minimizing current leakage. An exemplary input buffer cell described herein includes a first inverter stage with a pair of NMOS devices connected in series with a PMOS device and a second inverter stage having an additional PMOS device connected along a feedback path around an inverter. The PMOS device along the feedback path operates to assist the pair of NMOS devices to pull a voltage input to the inverter to a high logic state, when an input to the cell is held low, to prevent leakage current through the inverter. The pair of NMOS devices provide a first stage inverter substantially free of process variations. The PMOS device connected in series with the NMOS devices prevents current leakage through the NMOS devices when the input signal is held high.

摘要翻译： 集成电路包括具有地址路径的输入路径电路，该地址路径具有用于向寄存器提供地址信号的输入缓冲器。 具有输入缓冲器的单独的时钟路径提供用于对寄存器计时的时钟信号。 地址路径和时钟路径的输入缓冲器包括被配置为减少由过程变化引起的定时延迟差异同时最小化电流泄漏的输入缓冲器单元。 本文描述的示例性输入缓冲器单元包括具有与PMOS器件串联连接的一对NMOS器件的第一反相器级和具有沿着反相器周围的反馈路径连接的附加PMOS器件的第二反相器级。 沿着反馈路径的PMOS器件操作以在对单电池的输入保持为低电平时辅助NMOS对器件将逆变器的电压输入拉到高逻辑状态，以防止通过逆变器的漏电流。 这对NMOS器件提供基本上没有工艺变化的第一级逆变器。 与NMOS器件串联连接的PMOS器件防止当输入信号保持为高电平时通过NMOS器件的电流泄漏。

公开(公告)号：US6088289A

公开(公告)日：2000-07-11

申请号：US405950

申请日：1999-09-27

申请人： Greg J. Landry ,  Peter Adamek

发明人： Greg J. Landry ,  Peter Adamek

IPC分类号： G11C8/08 ,  G11C8/00

CPC分类号： G11C8/08

摘要： A circuit and method for controlling a wordline and/or stabilizing a memory cell comprising a first circuit and a second circuit. The first circuit may be configured to generate a control signal in response to (i) a select signal and (ii) an equalization signal. The second may be configured to generate an output signal in response to (i) the control signal and (ii) a global wordline signal. The output signal may be presented to one or more memory cells of a memory array.

摘要翻译： 一种用于控制字线和/或稳定包括第一电路和第二电路的存储单元的电路和方法。 第一电路可以被配置为响应于（i）选择信号和（ii）均衡信号而产生控制信号。 第二可以被配置为响应于（i）控制信号和（ii）全局字线信号而产生输出信号。 输出信号可以被呈现给存储器阵列的一个或多个存储器单元。

公开(公告)号：US5903174A

公开(公告)日：1999-05-11

申请号：US575554

申请日：1995-12-20

申请人： Greg J. Landry ,  Shailesh Shah ,  Ashish Pancholy

发明人： Greg J. Landry ,  Shailesh Shah ,  Ashish Pancholy

IPC分类号： H03K19/00 ,  H03K19/003 ,  H03K19/096

CPC分类号： H03K19/00323 ,  H03K19/0013

摘要： The integrated circuit includes an input path circuit with an address path having an input buffer for providing address signals to a register. A separate clock path having an input buffer provides a clock signal for clocking the register. The input path circuit also includes one or more decode units each having a number of logic gate cells such as NAND gate cells or NOR gate cells. Circuitry is provided within the logic gates for reducing timing delay differences between propagation of multiple bit binary signals, such as address signals, through the logic gates. In an exemplary NAND gate described herein, reduction in timing delay differences is achieved by positioning an additional PMOS device along a current path between a power source and an output path otherwise including only a pair of parallel PMOS devices. The additional PMOS device acts as a choke on the current flow through the pair of parallel PMOS devices thereby reducing propagation delay differences which would otherwise occur as a result of either only one or both of the parallel PMOS devices operating to pull up the output path. Similar circuit modifications are provided within NOR gates or logic gates.

摘要翻译： 集成电路包括具有地址路径的输入路径电路，该地址路径具有用于向寄存器提供地址信号的输入缓冲器。 具有输入缓冲器的单独的时钟路径提供用于对寄存器计时的时钟信号。 输入路径电路还包括一个或多个解码单元，每个解码单元具有多个逻辑门单元，例如NAND门单元或NOR门单元。 在逻辑门内提供电路，用于通过逻辑门减少诸如地址信号的多位二进制信号的传播之间的定时延迟差异。 在这里描述的示例性NAND门中，定时延迟差异的减小通过沿着电源和输出路径之间的电流路径定位另外的PMOS器件来实现，否则仅包括一对并联PMOS器件。 附加的PMOS器件用作通过该对并联PMOS器件的电流的扼流圈，从而减少由于只有一个或两个并联PMOS器件工作以上拉输出路径而导致的传播延迟差异。 在NOR门或逻辑门内提供类似的电路修改。

公开(公告)号：US06486712B1

公开(公告)日：2002-11-26

申请号：US09740106

申请日：2000-12-18

申请人： Greg J. Landry ,  Robert M. Reinschmidt ,  Timothy M. Lacey

发明人： Greg J. Landry ,  Robert M. Reinschmidt ,  Timothy M. Lacey

IPC分类号： H03K1700

CPC分类号： H03K17/063 ,  H03K17/693

摘要： A programmable switch includes at least one or more pass transistors having a control voltage that is greater than the data path reference voltage that is selected by a corresponding pass transistor. The control voltage is provided by a higher voltage power supply than the power supply that provides the data path reference voltage. In one embodiment, the higher voltage supply is a quiet supply that is not loaded with devices that switch during normal operation of the programmable switch such as CMOS devices. In another embodiment, the power supply that provides a voltage to an I/O circuit of the probable switch is the power supply that is utilized to provide the control voltage to the pass transistors. In a particular embodiment, the pass transistors comprise higher voltage tolerant devices than other devices in the programmable device. In a particular embodiment, the higher voltage supply is at least the data path reference voltage plus the threshold voltage of the pass transistors.

摘要翻译： 可编程开关包括至少一个或多个传输晶体管，其具有大于由对应的传输晶体管选择的数据路径参考电压的控制电压。 控制电压由提供数据路径参考电压的电源提供的高电压电源提供。 在一个实施例中，较高的电压源是无负载的装置，其可在诸如CMOS装置的可编程开关的正常操作期间切换。 在另一个实施例中，向可能开关的I / O电路提供电压的电源是用于向传输晶体管提供控制电压的电源。 在特定实施例中，传输晶体管包括比可编程器件中的其它器件更高的耐压器件。 在特定实施例中，较高电压源至少为数据通路参考电压加上通过晶体管的阈值电压。

公开(公告)号：US06333891B1

公开(公告)日：2001-12-25

申请号：US09613949

申请日：2000-07-11

申请人： Greg J. Landry ,  Peter Adamek

发明人： Greg J. Landry ,  Peter Adamek

IPC分类号： G11C800

CPC分类号： G11C8/08

摘要： A circuit and method for controlling a wordline and/or stabilizing a memory cell comprising a first circuit and a second circuit. The first circuit may be configured to generate a control signal in response to (i) a select signal and (i) an equalization signal. The second may be configured to generate an output signal in response to (i) the control signal and (ii) a global wordline signal. The output signal may be presented to one or more memory cells of a memory array.

摘要翻译： 一种用于控制字线和/或稳定包括第一电路和第二电路的存储单元的电路和方法。 第一电路可以被配置为响应于（i）选择信号和（i）均衡信号而产生控制信号。 第二可以被配置为响应于（i）控制信号和（ii）全局字线信号而产生输出信号。 输出信号可以被呈现给存储器阵列的一个或多个存储器单元。