公开(公告)号：US10965519B2

公开(公告)日：2021-03-30

申请号：US16283242

申请日：2019-02-22

Applicant: Tata Consultancy Services Limited

Inventor： Manoj Karunakaran Nambiar ,  Swapnil Rodi ,  Sunil Anant Puranik ,  Mahesh Damodar Barve

IPC: H04L12/24 ,  G06F11/20 ,  H04L12/26 ,  H04L29/08 ,  H04L29/06 ,  G06F11/07 ,  G06F16/245 ,  H04L29/14

Abstract: This disclosure relates generally to methods and systems for providing exactly-once transaction semantics for fault tolerant FPGA based transaction systems. The systems comprise middleware components in a server as well as client end. The server comprises Hosts and FPGAs. The FPGAs control transaction execution (the application processing logic also resides in the FPGA) and provide fault tolerance with high performance by means of a modified TCP implementation. The Hosts buffer and persist transaction records for failure recovery and achieving exactly-once transaction semantics. The monitoring and fault detecting components are distributed across the FPGA's and Hosts. Exactly-once transaction semantics is implemented without sacrificing performance by switching between a high performance mode and a conservative mode depending on component failures. PCIE switches for connectivity between FPGAs and Hosts ensure FPGAs are available even if Hosts fail. When FPGA's provide higher processing elements and memory, the Hosts may be eliminated.

公开(公告)号：US11212218B2

公开(公告)日：2021-12-28

申请号：US16535803

申请日：2019-08-08

Applicant: Tata Consultancy Services Limited

Inventor： Manoj Karunakaran Nambiar ,  Swapnil Rodi ,  Sunil Puranik ,  Mahesh Damodar Barve

IPC: H04L12/28 ,  H04L12/703 ,  H04L12/24 ,  H04L29/06

Abstract: The disclosure herein describes a method and a system for message based communication and failure recovery for FPGA middleware framework. A combination of FPGA and middleware framework provides a high throughput, low latency messaging and can reduce development time as most of the components can be re-used. Further the message based communication architecture built on a FPGA framework performs middleware activities that would enable reliable communication using TCP/UDP between different platforms regardless of their deployment. The proposed FPGA middleware framework provides for reliable communication of UDP based on TCP as well as failure recovery with minimum latency during a failover of an active FPGA framework during its operation, by using a passive FPGA in real-time and dynamic synchronization with the active FPGA.

公开(公告)号：US11263203B2

公开(公告)日：2022-03-01

申请号：US16663760

申请日：2019-10-25

Applicant: Tata Consultancy Services Limited

Inventor： Mahesh Damodar Barve ,  Sunil Anant Puranik ,  Manoj Nambiar ,  Swapnil Rodi

IPC: G06F16/23 ,  G06F16/901

Abstract: Data processing and storage is an important part of a number of applications. Conventional data processing and storage systems utilize either a full array structure or a full linked list structure for storing data wherein the array consumes large amount of memory and linked list provides slow processing. Thus, conventional systems and methods are not capable of providing simultaneous optimization of memory consumption and time efficiency. The present disclosure provides an efficient way of storing data by creating an integrated array and linked list based structure. The data is stored in the integrated array and linked list based structure by using a delta based mechanism. The delta based mechanism helps in determining the location in the integrated array and linked list based structure where the data should be stored. The present disclosure incorporates the advantages of both array and linked list structure resulting in reduced memory consumption and latency.

公开(公告)号：US11263164B1

公开(公告)日：2022-03-01

申请号：US17136734

申请日：2020-12-29

Applicant: Tata Consultancy Services Limited

Inventor： Mahesh Damodar Barve ,  Sunil Puranik ,  Swapnil Rodi ,  Manoj Nambiar ,  Dhaval Shah

IPC: G06F1/00 ,  G06F3/06 ,  G06F13/42 ,  G06F13/40 ,  H03K19/17728 ,  G06F9/54

Abstract: Conventionally, for processing multi-legged orders, matching engines were implemented in software and were connected through Ethernet which is very slow in terms of throughput. Such traditional trading systems failed to process orders of tokens on different machines and these were summarily rejected. Present disclosure provides multiple FPGA system being optimized for processing/executing multi-legged orders. The system includes a plurality of FPGAs which are interconnected for communication via a PCIe port of a multi-port PCIe switch. Each FPGA comprise a net processing layer, a matcher, and a look-up table. Each FPGA is configured to process tokens (e.g., securities, etc.). If orders to be processed are for tokens on same FPGA where the order is received, then tokens are processed locally. Else net processing layer of a specific FPGA routes to specific order request to another FPGA where the tokens (securities) are located thereby reducing the latency and improving overall throughput.