公开(公告)号：US11736594B2

公开(公告)日：2023-08-22

申请号：US17349085

申请日：2021-06-16

Applicant: Tata Consultancy Services Limited

Inventor： Dhaval Shah ,  Sunil Puranik ,  Manoj Nambiar ,  Mahesh Damodar Barve ,  Ishtiyaque Shaikh ,  Piyush Manavar ,  Sharyu Vijay Mukhekar

IPC: G06F15/173 ,  H04L69/16

CPC classification number: H04L69/16

Abstract: A method and system of a low-latency FPGA framework based on reliable UDP and TCP re-assembly middleware is disclosed. The need for low-latency communication in digital systems has increased drastically. The disclosed FPGA framework enables low-latency communication as a hybrid framework that supports both UDP & TCP communication. As known in art, TCP provides error checking support hence making TCP more reliable as compared to UDP, while UDP is faster but not reliable. Hence the disclosed low-latency FPGA framework latency utilizes the advantage of both UDP and TCP by utilizing UDP for its speed, while switching to TCP in case of a missing sequence in UDP. Further, the disclosed system proposes a TCP re-assembly middleware architecture for processing TCP with a lower-latency, wherein the TCP re-assembly middleware is an independent middleware that is a modular and a plug-play independent middleware.

公开(公告)号：US11449413B2

公开(公告)日：2022-09-20

申请号：US17345166

申请日：2021-06-11

Applicant: Tata Consultancy Services Limited

Inventor： Rekha Singhal ,  Gautam Shroff ,  Dheeraj Chahal ,  Mayank Mishra ,  Shruti Kunde ,  Manoj Nambiar

IPC: G06F11/36 ,  G06N3/02 ,  G06K9/62 ,  G06F9/48 ,  G06F40/20

Abstract: This disclosure relates generally to accelerating development and deployment of enterprise applications where the applications involve both data driven and task driven components in data driven enterprise information technology (IT) systems. The disclosed system is capable of determining components of the application that may be task-driven and/or those components which may be data-driven using inputs such as business use case, data sources and requirements specifications. The system is capable of determining the components that may be developed using task-driven and data-drive paradigms and enables migration of components from the task driven paradigm to the data driven paradigm. Also, the system trains a reinforcement learning (RL) model for facilitating migration of the identified components from the task driven paradigm to the data driven paradigm. The system is further capable of integrating the migrated and existing components to accelerate development and deployment an integrated IT application.

公开(公告)号：US11748292B2

公开(公告)日：2023-09-05

申请号：US17491689

申请日：2021-10-01

Applicant: Tata Consultancy Services Limited

Inventor： Piyush Manavar ,  Manoj Nambiar

IPC: G06F13/36 ,  G06F13/42 ,  G06N20/20

CPC classification number: G06F13/4221 ,  G06N20/20 ,  G06F2213/0026

Abstract: Various embodiments disclosed herein provides method and system for low latency FPGA based system for inference such as recommendation models. Conventional models for inference have high latency and low throughput in decision making models/processes. The disclosed method and system exploits parallelism in processing of XGB models and hence enables minimum possible latency and maximum possible throughput. Additionally, the disclosed system uses a trained model that is (re)trained using only those features which the model had used during training, remaining features are discarded during retraining of the model. The use of such selected set of features thus leads to reduction in the size of digital circuit significantly for the hardware implementation, thereby greatly enhancing the system performance.

公开(公告)号：US11640542B2

公开(公告)日：2023-05-02

申请号：US16359951

申请日：2019-03-20

Applicant: Tata Consultancy Services Limited

Inventor： Shruti Kunde ,  Chetan Phalak ,  Rekha Singhal ,  Manoj Nambiar

IPC: G06N5/02 ,  G06F16/9035 ,  G06N7/00 ,  G06N5/022

Abstract: The disclosure generally relates to system architectures, and, more particularly, to a method and system for system architecture recommendation. In existing scenario, a solution architect often gets minimum details about requirements, hence struggles to design a system architecture that matches the requirements. The method and system disclosed herein are to provide system recommendation in response to requirements provided as input to the system. The system generates an acyclic dependency graph based on parameters and values extracted from an obtained user input. The system then identifies a reference architectures that matches the requirements, and further selects components that match the architecture requirements. The system further selects technologies considering inter-operability of the technologies. Further, the system generates architecture recommendations for the user, based on the selected components, and technologies. The system can collect user feedback for to the recommendation provided, and can generate rankings to improve future recommendations.

公开(公告)号：US20220092354A1

公开(公告)日：2022-03-24

申请号：US17471564

申请日：2021-09-10

Applicant: Tata Consultancy Services Limited

Inventor： Shruti Kunde ,  Mayank Mishra ,  Rekha Singhal ,  Amey Pandit ,  Manoj Nambiar ,  Gautam Shroff

IPC: G06K9/62 ,  G06N20/00

Abstract: This disclosure relates generally to a method and system for generating labelled dataset using a training data recommender technique. Recommender systems face major challenges in handling dynamic data on machine learning paradigms thereby rendering inaccurate unlabeled dataset. The method of the present disclosure is based on a training data recommender technique suitably constructed with a newly defined parameter such as the labelled data prediction threshold to determine the adequate amount of labelled training data required for training the one or more machine learning models. The method processes the received unlabeled dataset for labelling the unlabeled dataset based on a labelled data prediction threshold which is determined using a trained training data recommender technique. This labelling data threshold leads to a significant reduction in training time while performing the one or more machine learning models and thus recommender systems to quickly adapt disruptions thereby decreasing the reduction factor.

公开(公告)号：US11263203B2

公开(公告)日：2022-03-01

申请号：US16663760

申请日：2019-10-25

Applicant: Tata Consultancy Services Limited

Inventor： Mahesh Damodar Barve ,  Sunil Anant Puranik ,  Manoj Nambiar ,  Swapnil Rodi

IPC: G06F16/23 ,  G06F16/901

Abstract: Data processing and storage is an important part of a number of applications. Conventional data processing and storage systems utilize either a full array structure or a full linked list structure for storing data wherein the array consumes large amount of memory and linked list provides slow processing. Thus, conventional systems and methods are not capable of providing simultaneous optimization of memory consumption and time efficiency. The present disclosure provides an efficient way of storing data by creating an integrated array and linked list based structure. The data is stored in the integrated array and linked list based structure by using a delta based mechanism. The delta based mechanism helps in determining the location in the integrated array and linked list based structure where the data should be stored. The present disclosure incorporates the advantages of both array and linked list structure resulting in reduced memory consumption and latency.

公开(公告)号：US20230412714A1

公开(公告)日：2023-12-21

申请号：US18335229

申请日：2023-06-15

Applicant: Tata Consultancy Services Limited

Inventor： Dhaval SHAH ,  Manoj Nambiar ,  Ishtiyaque Shaikh

IPC: H04L69/321 ,  H04L69/16

CPC classification number: H04L69/321 ,  H04L69/161

Abstract: This disclosure relates to time sensitive processing of TCP segments into application layer messages in FPGA. Certain applications such as “stock market” or “ticket booking system” require a time sensitive ordering of the transaction, as the timing of arrival of transaction (packet) will impact the result, wherein the time sensitive ordering occurs when a first packet reaching the application network is processed first or the processing of packets by the server is guaranteed in the order of packets received. However, the existing systems do not honor the time due to the layered network stack. The disclosure is a design and implementation of a middleware framework on FPGA platform which delivers messages to the application in the order in which they arrive. The disclosure enables time sensitive analysis of each message of the TCP segment based on the session-based information to re-assemble the plurality of messages in a time-sensitive queue.

公开(公告)号：US11669314B2

公开(公告)日：2023-06-06

申请号：US17562378

申请日：2021-12-27

Applicant: Tata Consultancy Services Limited

Inventor： Nupur Sumeet ,  Manoj Nambiar

IPC: G06F8/51 ,  G06F8/10 ,  G06F8/30 ,  G06F8/41 ,  G06F30/327

CPC classification number: G06F8/51 ,  G06F8/10 ,  G06F8/315 ,  G06F8/458 ,  G06F30/327

Abstract: This disclosure generally relates to high-level synthesis (HLS) platforms, and, more particularly, enable print functionality in high-level synthesis (HLS) platforms. The recent availability FPGA-HLS is a great success due to availability of compilers for FPGAs as opposed to hardware description languages (HDLs) that requires special skills. However, the compilers within the HLS design platform includes limited support for all the standard libraries, wherein features like print functionality is not supported. The invention discloses techniques to enable print functionality in HLS design platforms based on source-to-source transformations and stream combining scheme. In addition to enabling print functionality, the invention also discloses a formatter technique to receive-format FPGA data into human interpretable data.

公开(公告)号：US11611638B2

公开(公告)日：2023-03-21

申请号：US17207786

申请日：2021-03-22

Applicant: Tata Consultancy Services Limited

Inventor： Dhaval Shah ,  Sunil Puranik ,  Manoj Nambiar ,  Mahesh Damodar Barve ,  Ishtiyaque Shaikh

IPC: H04L69/12 ,  H04L49/9057 ,  H04L69/166

Abstract: A method and system of a re-assembly middleware in FPGA for processing TCP segments into application layer messages is disclosed. In recent years, the communication speed in digital systems has increased drastically and thus has brought in a growing need to ensure a good/high performance from the FPGA services. The disclosure proposes a re-assembly middleware in the FPGA for processing TCP segments into application layer messages at a pre-defined frequency for a good/high performance. The pre-defined frequency is a high frequency performance feature of the re-assembly middleware, wherein the FPGA's implementation frequency is at atleast 300 MHz based on a memory optimization technique. The memory optimization technique includes several strategies such registering an output and slicing memories.

公开(公告)号：US11263164B1

公开(公告)日：2022-03-01

申请号：US17136734

申请日：2020-12-29

Applicant: Tata Consultancy Services Limited

Inventor： Mahesh Damodar Barve ,  Sunil Puranik ,  Swapnil Rodi ,  Manoj Nambiar ,  Dhaval Shah

IPC: G06F1/00 ,  G06F3/06 ,  G06F13/42 ,  G06F13/40 ,  H03K19/17728 ,  G06F9/54

Abstract: Conventionally, for processing multi-legged orders, matching engines were implemented in software and were connected through Ethernet which is very slow in terms of throughput. Such traditional trading systems failed to process orders of tokens on different machines and these were summarily rejected. Present disclosure provides multiple FPGA system being optimized for processing/executing multi-legged orders. The system includes a plurality of FPGAs which are interconnected for communication via a PCIe port of a multi-port PCIe switch. Each FPGA comprise a net processing layer, a matcher, and a look-up table. Each FPGA is configured to process tokens (e.g., securities, etc.). If orders to be processed are for tokens on same FPGA where the order is received, then tokens are processed locally. Else net processing layer of a specific FPGA routes to specific order request to another FPGA where the tokens (securities) are located thereby reducing the latency and improving overall throughput.