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    Inter-cluster communication module using the memory access network
    2.
    发明申请
    Inter-cluster communication module using the memory access network 有权
    群集间通信模块使用内存接入网

    公开(公告)号：US20060212663A1

    公开(公告)日：2006-09-21

    申请号：US11246115

    申请日：2005-10-11

    申请人： Tay-Jyi Lin ,  Pi-Chen Hsiao ,  Chih-Wei Liu ,  Chein-Wei Jen ,  I-Tao Liao ,  Po-Han Huang

    发明人： Tay-Jyi Lin ,  Pi-Chen Hsiao ,  Chih-Wei Liu ,  Chein-Wei Jen ,  I-Tao Liao ,  Po-Han Huang

    IPC分类号： G06F12/00

    CPC分类号： G06F15/173

    摘要： An inter-cluster communication module using the memory access network is provided, including a plurality of clusters, a memory subsystem, a controller and a switch device. When some clusters issue a load instruction and some clusters issue a store instruction of an identical memory address concurrently, the controller controls the switch device which connects the clusters and the memory banks of the memory subsystem, so that the data item is transmitted from the cluster issuing the store instruction to the cluster issuing the load instruction through the switch device, thereby achieving data exchange between the clusters. Herein, the data item is selectively stored in the memory module depending on the address. Furthermore, the data item is also transmitted between the memory and the clusters over the switch device.

    摘要翻译： 提供了使用存储器访问网络的集群间通信模块，包括多个集群，存储器子系统，控制器和交换设备。 当一些集群发出加载指令并且一些集群同时发出相同存储器地址的存储指令时，控制器控制连接存储器子系统的集群和存储器组的交换设备，从而从集群发送数据项 通过交换设备向发布加载指令的集群发出存储指令，由此实现集群之间的数据交换。 这里，数据项根据地址被选择性地存储在存储器模块中。 此外，数据项也通过交换设备在存储器和簇之间传输。

    Inter-cluster communication module using the memory access network
    3.
    发明授权
    Inter-cluster communication module using the memory access network 有权
    群集间通信模块使用内存接入网

    公开(公告)号：US07404048B2

    公开(公告)日：2008-07-22

    申请号：US11246115

    申请日：2005-10-11

    申请人： Tay-Jyi Lin ,  Pi-Chen Hsiao ,  Chih-Wei Liu ,  Chein-Wei Jen ,  I-Tao Liao ,  Po-Han Huang

    发明人： Tay-Jyi Lin ,  Pi-Chen Hsiao ,  Chih-Wei Liu ,  Chein-Wei Jen ,  I-Tao Liao ,  Po-Han Huang

    IPC分类号： G06F12/00

    CPC分类号： G06F15/173

    摘要： An inter-cluster communication module using the memory access network is provided, including a plurality of clusters, a memory subsystem, a controller and a switch device. When some clusters issue a load instruction and some clusters issue a store instruction of an identical memory address concurrently, the controller controls the switch device which connects the clusters and the memory banks of the memory subsystem, so that the data item is transmitted from the cluster issuing the store instruction to the cluster issuing the load instruction through the switch device, thereby achieving data exchange between the clusters. Herein, the data item is selectively stored in the memory module depending on the address. Furthermore, the data item is also transmitted between the memory and the clusters over the switch device.

    摘要翻译： 提供了使用存储器访问网络的集群间通信模块，包括多个集群，存储器子系统，控制器和交换设备。 当一些集群发出加载指令并且一些集群同时发出相同存储器地址的存储指令时，控制器控制连接存储器子系统的集群和存储器组的交换设备，从而从集群发送数据项 通过交换设备向发布加载指令的集群发出存储指令，从而实现集群之间的数据交换。 这里，数据项根据地址被选择性地存储在存储器模块中。 此外，数据项也通过交换设备在存储器和簇之间传输。

    Static floating point arithmetic unit for embedded digital signals processing and control method thereof
    6.
    发明申请
    Static floating point arithmetic unit for embedded digital signals processing and control method thereof 审中-公开
    静态浮点运算单元，用于嵌入式数字信号处理及其控制方法

    公开(公告)号：US20050223053A1

    公开(公告)日：2005-10-06

    申请号：US10928150

    申请日：2004-08-30

    申请人： Tay-Jyi Lin ,  Hung-Yueh Lin ,  Chein-Wei Jen ,  Chih-Wei Liu ,  I-Tao Liao

    发明人： Tay-Jyi Lin ,  Hung-Yueh Lin ,  Chein-Wei Jen ,  Chih-Wei Liu ,  I-Tao Liao

    IPC分类号： G06F5/01 ,  G06F7/38 ,  G06F7/485 ,  G06F7/487 ,  G06F7/499 ,  G06F7/57

    CPC分类号： G06F7/483 ,  G06F5/012 ,  G06F7/485 ,  G06F7/4876 ,  G06F7/49936

    摘要： A floating point arithmetic unit for embedded digital signal processing is provided with the ability of tracking the exponent portion of numerals using static analyzing technology efficiently and of low-power consumption. A fix adding unit with a simplified mantissa alignment device and simplified normalizing device arranged at the input end and output end, a fix multiplying unit with a simplified normalizing device arranged at the output end, and a shifter are included in the floating point arithmetic unit. A shift control method in accordance the floating point arithmetic unit is also provided to prevent overflow of the peak of the numerals. According the unit and the method, the effective precision of the arithmetic result is higher. The hardware configuration, power consumption and chip area are similar with fix point arithmetic units, while the precision is close to the floating point arithmetic units with complicated configuration.

    摘要翻译： 用于嵌入式数字信号处理的浮点算术单元具有使用静态分析技术有效地跟踪低功耗的数字指数部分的能力。 具有简化的尾数对准装置的固定添加单元和布置在输入端和输出端的简化的归一化装置，具有布置在输出端的简化归一化装置的固定倍增单元和移位器包括在浮点运算单元中。 还提供了根据浮点运算单元的移位控制方法，以防止数字的峰值溢出。 根据单位和方法，算术结果的有效精度较高。 硬件配置，功耗和芯片面积与固定点算术单元相似，精度接近于配置复杂的浮点运算单元。

    Dynamically reconfigurable stages pipelined datapath with data valid signal controlled multiplexer
    7.
    发明授权
    Dynamically reconfigurable stages pipelined datapath with data valid signal controlled multiplexer 有权
    动态可重构级流水线数据通路与数据有效信号控制多路复用器

    公开(公告)号：US07406588B2

    公开(公告)日：2008-07-29

    申请号：US11229616

    申请日：2005-09-20

    申请人： Tay-Jyi Lin ,  Chein-Wei Jen ,  Chih-Wei Liu ,  Po-Han Huang ,  Wei-Sheng Huang ,  Chan-Hao Chang

    发明人： Tay-Jyi Lin ,  Chein-Wei Jen ,  Chih-Wei Liu ,  Po-Han Huang ,  Wei-Sheng Huang ,  Chan-Hao Chang

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3869

    摘要： A pipelined datapath with dynamically reconfigurable pipeline stages is provided, having a pipeline controller which generates clock signals and selects signals based on a system clock and a valid data signal to control each of the registers and each of the multiplexers in the pipeline circuit. In other words, when a valid datum is being processed, the pipeline register is activated to latch the output of the combinational logic circuit; otherwise, when an invalid datum is received, the register is not activated and the datum bypasses the register through a multiplexer. Therefore, the pipeline stages of the pipelined datapath are dynamically reconfigured to save the power dissipation effectively.

    摘要翻译： 提供了具有动态可重构流水线级的流水线数据路径，具有管线控制器，其生成时钟信号并基于系统时钟和有效数据信号选择信号，以控制流水线电路中的每个寄存器和多路复用器。 换句话说，当正在处理有效数据时，激活流水线寄存器来锁存组合逻辑电路的输出; 否则，当接收到无效数据时，寄存器不被激活，并且基准通过多路复用器旁路寄存器。 因此，流水线数据路径的流水线级可动态重新配置，有效节省功耗。

    Pipelined datapath with dynamically reconfigurable pipeline stages
    8.
    发明申请
    Pipelined datapath with dynamically reconfigurable pipeline stages 有权
    具有动态可重构流水线阶段的流水线数据路径

    公开(公告)号：US20060259748A1

    公开(公告)日：2006-11-16

    申请号：US11229616

    申请日：2005-09-20

    申请人： Tay-Jyi Lin ,  Chein-Wei Jen ,  Chih-Wei Liu ,  Po-Han Huang ,  Wei-Sheng Huang ,  Chan-Hao Chang

    发明人： Tay-Jyi Lin ,  Chein-Wei Jen ,  Chih-Wei Liu ,  Po-Han Huang ,  Wei-Sheng Huang ,  Chan-Hao Chang

    IPC分类号： G06F9/44

    CPC分类号： G06F9/3869

    摘要： A pipelined datapath with dynamically reconfigurable pipeline stages is provided, having a pipeline controller which generates clock signals and selects signals based on a system clock and a valid data signal to control each of the registers and each of the multiplexers in the pipeline circuit. In other words, when a valid datum is being processed, the pipeline register is activated to latch the output of the combinational logic circuit; otherwise, when an invalid datum is received, the register is not activated and the datum bypasses the register through a multiplexer. Therefore, the pipeline stages of the pipelined datapath are dynamically reconfigured to save the power dissipation effectively.

    摘要翻译： 提供了具有动态可重构流水线级的流水线数据路径，具有管线控制器，其生成时钟信号并基于系统时钟和有效数据信号选择信号，以控制流水线电路中的每个寄存器和多路复用器。 换句话说，当正在处理有效数据时，激活流水线寄存器来锁存组合逻辑电路的输出; 否则，当接收到无效数据时，寄存器不被激活，并且基准通过多路复用器旁路寄存器。 因此，流水线数据路径的流水线级可动态重新配置，有效节省功耗。

    Virtual Cluster Architecture And Method
    9.
    发明申请
    Virtual Cluster Architecture And Method 审中-公开
    虚拟集群架构与方法

    公开(公告)号：US20080162870A1

    公开(公告)日：2008-07-03

    申请号：US11780480

    申请日：2007-07-20

    申请人： Tay-Jyi Lin ,  Chein-Wei Jen ,  Pi-Chen Hsiao ,  Li-Chun Lin ,  Chih-Wei Liu

    发明人： Tay-Jyi Lin ,  Chein-Wei Jen ,  Pi-Chen Hsiao ,  Li-Chun Lin ,  Chih-Wei Liu

    IPC分类号： G06F15/00

    CPC分类号： G06F9/3824 ,  G06F9/3828 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3891

    摘要： Disclosed is a virtual cluster architecture and method. The virtual cluster architecture includes N virtual clusters, N register files, M sets of function units, a virtual cluster control switch, and an inter-cluster communication mechanism. This invention uses a way of time sharing or time multiplexing to alternatively execute a single program thread across multiple parallel clusters. It minimizes the hardware resources for complicated forwarding circuitry or bypassing mechanism by greatly increasing the tolerance of instruction latency in the datapath. This invention may distribute function units serially into pipeline stages to support composite instructions. The performance and the code sizes of application programs can therefore be significantly improved with these composite instructions, of which the introduced latency can be completely hidden in this invention. This invention also has the advantage of being compatible with the program codes developed on conventional multi-cluster architectures.

    摘要翻译： 公开了一种虚拟集群架构和方法。 虚拟集群架构包括N个虚拟集群，N个寄存器文件，M个功能单元组，一个虚拟集群控制交换机和一个集群间通信机制。 本发明使用时间共享或时间复用的方式来交替地在多个并行簇上执行单个程序线程。 它通过大大增加数据路径中指令延迟的容限，最大限度地减少了复杂转发电路或旁路机制的硬件资源。 本发明可以将功能单元串行地分配到流水线阶段以支持复合指令。 因此，通过这些复合指令可以显着改善应用程序的性能和代码大小，其中引入的延迟可以完全隐藏在本发明中。 本发明还具有与常规多集群架构上开发的程序代码兼容的优点。

    Method for inter-cluster communication that employs register permutation
    10.
    发明申请
    Method for inter-cluster communication that employs register permutation 审中-公开
    采用寄存器排列的集群间通信方法

    公开(公告)号：US20050204118A1

    公开(公告)日：2005-09-15

    申请号：US10787211

    申请日：2004-02-27

    申请人： Chein-Wei Jen ,  Tay-Jyi Lin ,  Chen-Chia Lee ,  Chin-Chi Chang ,  Chih-Wei Liu

    发明人： Chein-Wei Jen ,  Tay-Jyi Lin ,  Chen-Chia Lee ,  Chin-Chi Chang ,  Chih-Wei Liu

    IPC分类号： G06F15/00

    CPC分类号： G06F9/30032 ,  G06F9/3012 ,  G06F9/3828 ,  G06F9/3891

    摘要： The present invention is a method for inter-cluster communication that employs register permutation by dynamically mapping the registers to the functional units. Because only the mapping between registers and functional units is changed and no actual data movement occurs, the present invention greatly diminishes the power consumption. Owing to the inter-cluster communication mechanism, a centralized register file can be replaced with small register sub-blocks, where the silicon area is greatly reduced, and the access time and the power consumption are also diminished.

    摘要翻译： 本发明是一种群间通信的方法，其通过将寄存器动态映射到功能单元来采用寄存器置换。 因为只有寄存器和功能单元之间的映射被改变并且没有发生实际的数据移动，所以本发明大大地降低了功耗。 由于集群间通信机制，集中式寄存器文件可以用小的寄存器子块代替，其中硅面积大大减少，访问时间和功耗也减少。