公开(公告)号：US10521237B2

公开(公告)日：2019-12-31

申请号：US14219030

申请日：2014-03-19

Applicant: Technion Research and Development Foundation LTD.

Inventor： Avinoam Kolodny ,  Uri Weiser ,  Shahar Kvatinsky

IPC: G06F9/38 ,  G06F9/30 ,  H01L45/00 ,  G06F9/46

Abstract: A method and a device that includes a set of multiple pipeline stages, wherein the set of multiple pipeline stages is arranged to execute a first thread of instructions; multiple memristor based registers that are arranged to store a state of another thread of instructions that differs from the first thread of instructions; and a control circuit that is arranged to control a thread switch between the first thread of instructions and the other thread of instructions by controlling a storage of a state of the first thread of instructions at the multiple memristor based registers and by controlling a provision of the state of the other thread of instructions by the set of multiple pipeline stages; wherein the set of multiple pipeline stages is arranged to execute the other thread of instructions upon a reception of the state of the other thread of instructions.

公开(公告)号：US20140325192A1

公开(公告)日：2014-10-30

申请号：US14219030

申请日：2014-03-19

Applicant: Technion Research and Development Foundation LTD.

Inventor： Avinoam Kolodny ,  Uri Weiser ,  Shahar Kvatinsky

IPC: G06F9/38 ,  G06F9/30

Abstract: A method and a device that includes a set of multiple pipeline stages, wherein the set of multiple pipeline stages is arranged to execute a first thread of instructions; multiple memristor based registers that are arranged to store a state of another thread of instructions that differs from the first thread of instructions; and a control circuit that is arranged to control a thread switch between the first thread of instructions and the other thread of instructions by controlling a storage of a state of the first thread of instructions at the multiple memristor based registers and by controlling a provision of the state of the other thread of instructions by the set of multiple pipeline stages; wherein the set of multiple pipeline stages is arranged to execute the other thread of instructions upon a reception of the state of the other thread of instructions.

Abstract translation: 一种包括一组多个流水线级的方法和装置，其中所述多个流水线级的组被布置为执行第一指令线程; 多个基于忆阻器的寄存器被布置为存储不同于第一指令线程的另一指令线程的状态; 以及控制电路，其被布置为通过控制在所述多个基于忆阻器的多个寄存器上的所述第一指令线程的状态的存储来控制所述第一指令线程和所述另一指令线程之间的线程切换，并且通过控制所述指令的提供 状态的另一个线程的指令由多个流水线级组组成; 其中所述多个流水线级的集合被布置为在接收到另一线程指令的状态时执行另一指令线程。