公开(公告)号：US09659650B2

公开(公告)日：2017-05-23

申请号：US15119185

申请日：2015-02-17

Applicant: Technion Research and Development Foundation LTD. ,  UNIVERSITY OF ROCHESTER

Inventor： Avinoam Kolodny ,  Shahar Kvatinsky ,  Ravi Patel ,  Eby Friedman

IPC: G11C11/00 ,  G11C13/00 ,  G06F9/30 ,  H01L27/24

CPC classification number: G11C13/0069 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/30141 ,  G06F9/3851 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/004 ,  G11C14/009 ,  H01L27/24

Abstract: A multistate register, comprising: a flip-flop that comprises a first latch, a second latch and an intermediate gate coupled between the first and second latches; multiple memristive devices; and an interface coupled between the multiple memristive devices and the flip-flop; wherein the multistate register is arranged to operate in a memristive device write mode, in a memristive device read mode and in a flip-flop mode; wherein when operating in the memristive device read mode, the interface is arranged to write to a first selected memristive device of the multiple memristive devices a first logic value stored in the first latch; wherein when operating in the memristive device write mode, the interface is arranged to write to the second latch a second logic value stored in a second selected memristive device of the multiple memristive devices; and wherein when operating on a flip-flop mode logic the interface is prevented from transferring values between the flip flop and the memristive devices.

公开(公告)号：US09754203B2

公开(公告)日：2017-09-05

申请号：US14219007

申请日：2014-03-19

Applicant: Technion Research and Development Foundation LTD.

Inventor： Dotan Di Castro ,  Daniel Soudry ,  Shahar Kvatinsky ,  Asaf Gal ,  Avinoam Kolodny

IPC: G06N3/063 ,  G06N3/04 ,  G06G7/163

CPC classification number: G06N3/0635 ,  G06G7/163 ,  G06N3/049

Abstract: A device, comprising: an array of cells, wherein the cells are arranged in columns and rows; wherein each cell comprises a memristive device; an interfacing circuit that is coupled to each cell of the array of cells; wherein the interfacing circuit is arranged to: receive or generate first variables and second variables; generate memristive device input signals that once provided to memristive devices of the array will cause a change in a state variable of each of the memristive devices of the cells of the array, wherein the change in the state variable of each of the memristive devices of the cells of array reflects a product of one of the first variables and one of the second variables; provide the memristive device input signals to memristive devices of the array; and receive output signals that are a function of at least products of the first variables and the second variables.

公开(公告)号：US09548741B1

公开(公告)日：2017-01-17

申请号：US14798485

申请日：2015-07-14

Applicant: Technion Research and Development Foundation LTD.

Inventor： Shahar Kvatinsky ,  Avinoam Kolodny ,  Yifat Hanein

IPC: H03K19/173 ,  H03K19/177 ,  H03K19/02 ,  H03K19/094

CPC classification number: H03K19/1776 ,  G11C13/0007 ,  H03K19/02 ,  H03K19/094 ,  H03K19/17708

Abstract: A device that includes a memristive Akers logic array, wherein the memristive Akers logic array comprises multiple primitive logic cells that are coupled to each other; wherein each primitive logic cell comprises at least one memristive device.

Abstract translation: 一种包括忆阻阿克斯逻辑阵列的装置，其中忆阻Akers逻辑阵列包括彼此耦合的多个基本逻辑单元; 其中每个基元逻辑单元包括至少一个忆阻器件。

公开(公告)号：US10521237B2

公开(公告)日：2019-12-31

申请号：US14219030

申请日：2014-03-19

Applicant: Technion Research and Development Foundation LTD.

Inventor： Avinoam Kolodny ,  Uri Weiser ,  Shahar Kvatinsky

IPC: G06F9/38 ,  G06F9/30 ,  H01L45/00 ,  G06F9/46

Abstract: A method and a device that includes a set of multiple pipeline stages, wherein the set of multiple pipeline stages is arranged to execute a first thread of instructions; multiple memristor based registers that are arranged to store a state of another thread of instructions that differs from the first thread of instructions; and a control circuit that is arranged to control a thread switch between the first thread of instructions and the other thread of instructions by controlling a storage of a state of the first thread of instructions at the multiple memristor based registers and by controlling a provision of the state of the other thread of instructions by the set of multiple pipeline stages; wherein the set of multiple pipeline stages is arranged to execute the other thread of instructions upon a reception of the state of the other thread of instructions.

公开(公告)号：US20170019108A1

公开(公告)日：2017-01-19

申请号：US14798485

申请日：2015-07-14

Applicant: Technion Research and Development Foundation LTD.

Inventor： Shahar Kvatinsky ,  Avinoam Kolodny ,  Yifat Hanein

IPC: H03K19/177 ,  H03K19/094 ,  H03K19/02

CPC classification number: H03K19/1776 ,  G11C13/0007 ,  H03K19/02 ,  H03K19/094 ,  H03K19/17708

Abstract: A device that includes a memristive Akers logic array, wherein the memristive Akers logic array comprises multiple primitive logic cells that are coupled to each other; wherein each primitive logic cell comprises at least one memristive device.

Abstract translation: 一种包括忆阻阿克斯逻辑阵列的装置，其中忆阻Akers逻辑阵列包括彼此耦合的多个基本逻辑单元; 其中每个基元逻辑单元包括至少一个忆阻器件。

公开(公告)号：US20170011797A1

公开(公告)日：2017-01-12

申请号：US15119185

申请日：2015-02-17

Applicant: TECHNION RESEARCH AND DEVELOPMENT FOUNDATION LTD. ,  UNIVERSITY OF ROCHESTER

Inventor： Avinoam Kolodny ,  Shahar Kvatinsky ,  Ravi Patel ,  Eby Friedman

IPC: G11C13/00 ,  G06F9/30

CPC classification number: G11C13/0069 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/30141 ,  G06F9/3851 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/004 ,  G11C14/009 ,  H01L27/24

Abstract: A multistate register, comprising: a flip-flop that comprises a first latch, a second latch and an intermediate gate coupled between the first and second latches; multiple memristive devices; and an interface coupled between the multiple memristive devices and the flip-flop; wherein the multistate register is arranged to operate in a memristive device write mode, in a memristive device read mode and in a flip-flop mode; wherein when operating in the memristive device read mode, the interface is arranged to write to a first selected memristive device of the multiple memristive devices a first logic value stored in the first latch; wherein when operating in the memristive device write mode, the interface is arranged to write to the second latch a second logic value stored in a second selected memristive device of the multiple memristive devices; and wherein when operating on a flip-flop mode logic the interface is prevented from transferring values between the flip flop and the memristive devices.

Abstract translation: 一种多态寄存器，包括：触发器，包括第一锁存器，第二锁存器和耦合在所述第一和第二锁存器之间的中间栅极; 多个忆阻器 以及耦合在所述多个忆阻器件和所述触发器之间的接口; 其中所述多态寄存器被布置成以忆阻器件读取模式和触发器模式在忆阻器件写入模式下工作; 其中当在所述忆阻器件读取模式下操作时，所述接口被布置为向所述多个忆阻器件的第一选择的忆阻器件写入存储在所述第一锁存器中的第一逻辑值; 其中当在所述忆阻器件写入模式下操作时，所述接口被布置为向所述第二锁存器写入存储在所述多个忆阻器件的第二选择的忆阻器中的第二逻辑值; 并且其中当在触发器模式逻辑上操作时，防止接口在触发器和忆阻器之间传送值。

公开(公告)号：US20140325192A1

公开(公告)日：2014-10-30

申请号：US14219030

申请日：2014-03-19

Applicant: Technion Research and Development Foundation LTD.

Inventor： Avinoam Kolodny ,  Uri Weiser ,  Shahar Kvatinsky

IPC: G06F9/38 ,  G06F9/30

Abstract: A method and a device that includes a set of multiple pipeline stages, wherein the set of multiple pipeline stages is arranged to execute a first thread of instructions; multiple memristor based registers that are arranged to store a state of another thread of instructions that differs from the first thread of instructions; and a control circuit that is arranged to control a thread switch between the first thread of instructions and the other thread of instructions by controlling a storage of a state of the first thread of instructions at the multiple memristor based registers and by controlling a provision of the state of the other thread of instructions by the set of multiple pipeline stages; wherein the set of multiple pipeline stages is arranged to execute the other thread of instructions upon a reception of the state of the other thread of instructions.

Abstract translation: 一种包括一组多个流水线级的方法和装置，其中所述多个流水线级的组被布置为执行第一指令线程; 多个基于忆阻器的寄存器被布置为存储不同于第一指令线程的另一指令线程的状态; 以及控制电路，其被布置为通过控制在所述多个基于忆阻器的多个寄存器上的所述第一指令线程的状态的存储来控制所述第一指令线程和所述另一指令线程之间的线程切换，并且通过控制所述指令的提供 状态的另一个线程的指令由多个流水线级组组成; 其中所述多个流水线级的集合被布置为在接收到另一线程指令的状态时执行另一指令线程。

公开(公告)号：US20140289179A1

公开(公告)日：2014-09-25

申请号：US14219007

申请日：2014-03-19

Applicant: Technion Research and Development Foundation LTD.

Inventor： Dotan Di Castro ,  Daniel Soudry ,  Shahar Kvatinsky ,  Asaf Gal ,  Avinoam Kolodny

IPC: G06N3/08 ,  G06N3/063

CPC classification number: G06N3/0635 ,  G06G7/163 ,  G06N3/049

Abstract: A device, comprising: an array of cells, wherein the cells are arranged in columns and rows; wherein each cell comprises a memristive device; an interfacing circuit that is coupled to each cell of the array of cells; wherein the interfacing circuit is arranged to: receive or generate first variables and second variables; generate memristive device input signals that once provided to memristive devices of the array will cause a change in a state variable of each of the memristive devices of the cells of the array, wherein the change in the state variable of each of the memristive devices of the cells of array reflects a product of one of the first variables and one of the second variables; provide the memristive device input signals to memristive devices of the array; and receive output signals that are a function of at least products of the first variables and the second variables;

Abstract translation: 一种设备，包括：单元阵列，其中所述单元被排列成列和行; 其中每个单元包括忆阻器件; 耦合到所述单元阵列的每个单元的接口电路; 其中所述接口电路被布置成：接收或生成第一变量和第二变量; 产生一旦提供给阵列的忆阻器件的忆阻器件输入信号将导致阵列单元的每个忆阻器件的状态变量的改变，其中每个复位器件的状态变量的改变 数组的单元反映了第一个变量之一和第二个变量之一的乘积; 提供忆阻器件输入信号到阵列的忆阻器件; 并且接收至少是所述第一变量和所述第二变量的乘积的函数的输出信号;