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公开(公告)号：US20160224465A1
公开(公告)日：2016-08-04
申请号：US14989880
申请日：2016-01-07
Inventor： Amir Morad , Leonid Yavits , Shahar Kvatinsky , Ran Ginosar
CPC classification number: G06F9/3887 , G06F1/3293 , G06F9/30087 , G06F9/3877 , G06F12/0207 , G06F12/0897 , G06F15/7825 , G06F15/8007 , Y02D10/122
Abstract: A hybrid computer that comprises a sequential processor, a single instruction massively parallel (SIMD) processor, and shared memory module that is shared between the sequential processor and the SIMD processor.
Abstract translation: 一种混合计算机，其包括顺序处理器，单指令大规模并行（SIMD）处理器和在顺序处理器和SIMD处理器之间共享的共享存储器模块。
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公开(公告)号：US20150256178A1
公开(公告)日：2015-09-10
申请号：US14641482
申请日：2015-03-09
Inventor： Shahar Kvatinsky , Dmitry Belousov , Slavik Liman , Nimrod Wald , Guy Satat
IPC: H03K19/003 , H03K19/00 , H03K19/08
CPC classification number: H03K19/00346 , H03K19/0021 , H03K19/02 , H03K19/0813 , H03K19/177
Abstract: According to an embodiment of the invention there is provided a device and method. The device may include a pure memristive logic gate, wherein the pure memristive logic gate consists essentially of at least one input memristive device and an output memristive device that is coupled to and differs from the at least one memristive device; wherein the pure memristive device is controlled by a single control voltage.
Abstract translation: 根据本发明的实施例，提供了一种装置和方法。 该装置可以包括纯粹的忆阻逻辑门，其中纯忆忆性逻辑门基本上由至少一个输入忆阻器件和输出忆阻器件组成，该器件与至少一个忆阻器件耦接并不同; 其中纯粹的忆阻器由单个控制电压控制。
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公开(公告)号：US10996959B2
公开(公告)日：2021-05-04
申请号：US14989880
申请日：2016-01-07
Inventor： Amir Morad , Leonid Yavits , Shahar Kvatinsky , Ran Ginosar
IPC: G06F12/00 , G06F9/38 , G06F15/167 , G06F1/3293 , G06F15/78 , G06F9/30 , G06F13/00 , G06F13/28 , G06F15/80 , G06F12/0897 , G06F12/02
Abstract: A hybrid computer that comprises a sequential processor, a single instruction massively parallel (SIMD) processor, and shared memory module that is shared between the sequential processor and the SIMD processor.
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公开(公告)号：US09754203B2
公开(公告)日：2017-09-05
申请号：US14219007
申请日：2014-03-19
Inventor： Dotan Di Castro , Daniel Soudry , Shahar Kvatinsky , Asaf Gal , Avinoam Kolodny
CPC classification number: G06N3/0635 , G06G7/163 , G06N3/049
Abstract: A device, comprising: an array of cells, wherein the cells are arranged in columns and rows; wherein each cell comprises a memristive device; an interfacing circuit that is coupled to each cell of the array of cells; wherein the interfacing circuit is arranged to: receive or generate first variables and second variables; generate memristive device input signals that once provided to memristive devices of the array will cause a change in a state variable of each of the memristive devices of the cells of the array, wherein the change in the state variable of each of the memristive devices of the cells of array reflects a product of one of the first variables and one of the second variables; provide the memristive device input signals to memristive devices of the array; and receive output signals that are a function of at least products of the first variables and the second variables.
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公开(公告)号：US09548741B1
公开(公告)日：2017-01-17
申请号：US14798485
申请日：2015-07-14
Inventor： Shahar Kvatinsky , Avinoam Kolodny , Yifat Hanein
IPC: H03K19/173 , H03K19/177 , H03K19/02 , H03K19/094
CPC classification number: H03K19/1776 , G11C13/0007 , H03K19/02 , H03K19/094 , H03K19/17708
Abstract: A device that includes a memristive Akers logic array, wherein the memristive Akers logic array comprises multiple primitive logic cells that are coupled to each other; wherein each primitive logic cell comprises at least one memristive device.
Abstract translation: 一种包括忆阻阿克斯逻辑阵列的装置，其中忆阻Akers逻辑阵列包括彼此耦合的多个基本逻辑单元; 其中每个基元逻辑单元包括至少一个忆阻器件。
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Patent Agency Ranking
公开(公告)号：US10284203B2
公开(公告)日：2019-05-07
申请号：US15622090
申请日：2017-06-14
Inventor： Shahar Kvatinsky , Dmitry Belousov , Slavik Liman , Nimrod Wald , Guy Satat
Abstract: According to an embodiment of the invention there is provided a device and method. The device may include a pure memristive logic gate, wherein the pure memristive logic gate consists essentially of at least one input memristive device and an output memristive device that is coupled to and differs from the at least one memristive device; wherein the pure memristive device is controlled by a single control voltage.
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公开(公告)号：US09685954B2
公开(公告)日：2017-06-20
申请号：US14641482
申请日：2015-03-09
Inventor： Shahar Kvatinsky , Dmitry Belousov , Slavik Liman , Nimrod Wald , Guy Satat
IPC: H03K19/173 , H03K19/003 , H03K19/08 , H03K19/00
CPC classification number: H03K19/00346 , H03K19/0021 , H03K19/02 , H03K19/0813 , H03K19/177
Abstract: According to an embodiment of the invention there is provided a device and method. The device may include a pure memristive logic gate, wherein the pure memristive logic gate consists essentially of at least one input memristive device and an output memristive device that is coupled to and differs from the at least one memristive device; wherein the pure memristive device is controlled by a single control voltage.
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公开(公告)号：US09659650B2
公开(公告)日：2017-05-23
申请号：US15119185
申请日：2015-02-17
Inventor： Avinoam Kolodny , Shahar Kvatinsky , Ravi Patel , Eby Friedman
CPC classification number: G11C13/0069 , G06F9/30101 , G06F9/30123 , G06F9/30141 , G06F9/3851 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C14/009 , H01L27/24
Abstract: A multistate register, comprising: a flip-flop that comprises a first latch, a second latch and an intermediate gate coupled between the first and second latches; multiple memristive devices; and an interface coupled between the multiple memristive devices and the flip-flop; wherein the multistate register is arranged to operate in a memristive device write mode, in a memristive device read mode and in a flip-flop mode; wherein when operating in the memristive device read mode, the interface is arranged to write to a first selected memristive device of the multiple memristive devices a first logic value stored in the first latch; wherein when operating in the memristive device write mode, the interface is arranged to write to the second latch a second logic value stored in a second selected memristive device of the multiple memristive devices; and wherein when operating on a flip-flop mode logic the interface is prevented from transferring values between the flip flop and the memristive devices.
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公开(公告)号：US10521237B2
公开(公告)日：2019-12-31
申请号：US14219030
申请日：2014-03-19
Inventor： Avinoam Kolodny , Uri Weiser , Shahar Kvatinsky
Abstract: A method and a device that includes a set of multiple pipeline stages, wherein the set of multiple pipeline stages is arranged to execute a first thread of instructions; multiple memristor based registers that are arranged to store a state of another thread of instructions that differs from the first thread of instructions; and a control circuit that is arranged to control a thread switch between the first thread of instructions and the other thread of instructions by controlling a storage of a state of the first thread of instructions at the multiple memristor based registers and by controlling a provision of the state of the other thread of instructions by the set of multiple pipeline stages; wherein the set of multiple pipeline stages is arranged to execute the other thread of instructions upon a reception of the state of the other thread of instructions.
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公开(公告)号：US20180367149A1
公开(公告)日：2018-12-20
申请号：US15622090
申请日：2017-06-14
Inventor： Shahar Kvatinsky , Dmitry Belousov , Slavik Liman , Nimrod Wald , Guy Satat
CPC classification number: H03K19/20 , G11C13/0002 , G11C13/0069
Abstract: According to an embodiment of the invention there is provided a device and method. The device may include a pure memristive logic gate, wherein the pure memristive logic gate consists essentially of at least one input memristive device and an output memristive device that is coupled to and differs from the at least one memristive device; wherein the pure memristive device is controlled by a single control voltage.
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