DOUBLE QUADRATURE WITH ADAPTIVE PHASE SHIFT FOR IMPROVED PHASE REFERENCE PERFORMANCE
    1.
    发明申请
    DOUBLE QUADRATURE WITH ADAPTIVE PHASE SHIFT FOR IMPROVED PHASE REFERENCE PERFORMANCE 有权
    具有适应性相位移动的双重平衡改善相位参考性能

    公开(公告)号:US20160033309A1

    公开(公告)日:2016-02-04

    申请号:US14519370

    申请日:2014-10-21

    CPC classification number: G01D18/00 G01R13/0272 G01R31/31709

    Abstract: A method for correcting a timing error in a test and measurement instrument. The method includes receiving a clock signal at each of four samplers. The first clock signal is sampled at the first sampler at a first phase, the second clock signal is sampled at the second sampler at a second phase that is 90 degrees offset from the first phase, the third clock signal is sampled at the third sampler at a third phase that is 45 degrees offset from the first phase, and the fourth clock signal is sampled at the fourth sampler at a fourth phase that is 90 degrees offset from the third phase. Each of the outputs from the samplers are digitized and a timing correction is calculated based on the digitized outputs from the digitized outputs.

    Abstract translation: 一种用于校正测试和测量仪器中的定时误差的方法。 该方法包括在四个采样器中的每一个处接收时钟信号。 第一时钟信号在第一采样器处以第一相采样,第二时钟信号在第二采样器以与第一相位偏移90度的第二相位采样,第三时钟信号在第三采样器处采样, 第三相位与第一相位偏移45度,第四时钟信号在第四采样器处以与第三相位偏移90度的第四相位被采样。 来自采样器的每个输出被数字化,并且基于来自数字化输出的数字化输出来计算定时校正。

    Double quadrature with adaptive phase shift for improved phase reference performance

    公开(公告)号:US09909907B2

    公开(公告)日:2018-03-06

    申请号:US14519370

    申请日:2014-10-21

    CPC classification number: G01D18/00 G01R13/0272 G01R31/31709

    Abstract: A method for correcting a timing error in a test and measurement instrument. The method includes receiving a clock signal at each of four samplers. The first clock signal is sampled at the first sampler at a first phase, the second clock signal is sampled at the second sampler at a second phase that is 90 degrees offset from the first phase, the third clock signal is sampled at the third sampler at a third phase that is 45 degrees offset from the first phase, and the fourth clock signal is sampled at the fourth sampler at a fourth phase that is 90 degrees offset from the third phase. Each of the outputs from the samplers are digitized and a timing correction is calculated based on the digitized outputs from the digitized outputs.

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